Integrated Analog
The on-board 12-bit, 130 ksps differential Analog-to-Digital Converter (ADC) features selectable internal voltage references with minimal temperature drift. It can be used to improve noise suppression and accuracy for analog inputs its hardware averaging and oversampling. Its averaging and threshold detection enables the MCU to remain asleep for longer periods, significantly reducing power consumption. Using the Event System, the on-board Analog Comparator (AC) can be connected to trigger autonomous operation in other peripherals, which is ideal for real-time control and closed-loop operations. The output of the 10-bit Digital-to-Analog Converter (DAC) can either be sent to a pin or it can be used to generate an adjustable reference voltage for the AC

Analog Signal Conditioning (OPAMP)
The Analog Signal Conditioning (OPAMP) peripheral features three operational amplifiers (op amps). These op amps are implemented with a flexible connection scheme using analog multiplexers and resistor ladders. This allows a large number of analog signal conditioning configurations to be achieved, many of which require no external components

Multi Voltage I/O (MVIO)
The Multi Voltage I/O (MVIO) system powers Port C and allows it to operate at a different voltage than the rest of the device. This greatly simplifies communication with other devices that might be running at a different voltage without the need of expensive external level shifters. If voltage is dropped on the VDDIO2 pin, an interrupt can be issued notifying the main application that the MVIO system is currently unpowered and not able to operate. If you do not want to use MVIO, VDDIO2 should be connected to VDD.

Zero Cross Detect (ZCD)
The Zero Cross Detect module can monitor AC line voltage and indicate zero crossing activity. This information is made directly available to the on-board Waveform Generation peripherals for use in TRIAC control applications, greatly reducing both Central Processing Unit (CPU) demand and overall development cost by lowering the bill of materials.

Configurable Custom Logic (CCL)
The Configurable Custom Logic (CCL) is a programmable logic peripheral that can be connected to the device pins, events or other internal peripherals. Each Lookup Table (LUT) consists of three inputs: a truth table, an optional synchronizer and a filter and edge detector. An LUT can generate an output to be routed internally or to an I/O pin, which eliminates the need for external logic and reduces BOM cost.

Event System
The Event System allows peripherals to communicate directly with each other without involving the CPU or bus resources. The Event System’s network is independent of the traditional data bus paths. This means that different triggers at the peripheral level can result in an event, such as a timer’s interrupts triggering an action in another peripheral. The Event System has three independent channels for direct peripheral-to-peripheral signaling. This deterministic signaling method is a perfect fit for real-time applications. The events are handled at the peripheral level even if the CPU is occupied handling interrupts or in sleep mode.

On-Board Safety and Monitoring
You can use the built-in features that support safety-critical applications to add robustness and reliability to your design. These include the Windowed Watchdog Timer (WDT) for system supervision, the Cyclic Redundancy Check (CRC) for scanning Flash memory, and the Event System for fault detection. Other features include a Voltage Level Monitor (VLM), a Brown-Out Detector (BOD) and Power-On Reset (POR) for monitoring the supply voltage.

Cyclic Redundancy Check (CRC)
The Cyclic Redundancy Check (CRC) is used to verify that there is no corruption in the application code. It calculates the checksum of the entire Flash memory, or parts of it, and automatically compares it with the expected result. This enables it to quickly and efficiently detect errors in program memory. The CRC can scan at run time or it can run during reset to ensure that the Flash memory is valid before the CPU is allowed to execute the code. When it is done at run time, the CRC scan temporarily halts the CPU to quickly complete the scan.

Windowed Watchdog Timer (WWDT)
The Windowed Watchdog Timer (WWDT) is a system supervisory circuit that generates a reset if software anomalies, like runaway or deadlocked code, are detected within a configurable critical window. When enabled, the WWDT is a constantly running timer configured to a predefined timeout period. If the WWDT is not reset within the timeout period, it will issue a System Reset

Clock Failure Detect (CFD)
The Clock Failure Detect (CFD) is a system supervisory circuit that will switch over to the internal clock if the external crystal fails (stops). This additional safety level allows the device to run on a very precise clock. If the crystal fails, the device automatically switches to a secondary internal clock source and generates an interrupt to notify the main application that the external crystal has stopped. The user can then determine if the application needs to stop or go into a safe mode.

Power-On Reset (POR)
Safe startup of every device is essential. The Power-on Reset (POR) peripheral is used to generate a reset signal when a device is powered up to put it in a known state. It is also important that the device’s memories and digital logic have sufficient supply voltage to operate correctly. When the voltage rises, the POR is activated and will hold the device in reset until the voltage is above a fixed threshold value. The POR will remain enabled for as long as the device is powered.