The SMC 1000 8x25G serial memory controller enables CPUs and other compute-centric SoCs to utilize four times the memory channels of parallel attached DRAM within the same package footprint compared to DDR4. The SMC 1000 8x25G enables higher memory bandwidth and media independence for High Performance Computing (HPC), big data, artificial intelligence and machine learning compute-intensive applications with ultra-low latency.
The SMC 1000 8x25G interfaces to the CPU via a narrow 8-lane differential Open Memory Interface (OMI)-compliant 25 Gbps interface and bridges to memory via a wide 72-bit DDR4 3200 interface. It supports three DDR4 data rates—DDR4-2666, DDR4-2933, and DDR4-3200—resulting in a significant reduction in the required number of host CPU or SoC pins per DDR4 memory channel. This allows for more memory channels and, therefore, increases the available memory bandwidth. The SMC 1000 8x25G also features an innovative low-latency design, which enables memory systems to have virtually the identical bandwidth and latency performance as comparable LRDIMM products.
The SMC 1000 8x25G combines data and address into one unified chip as compared to LRDIMM, which utilizes an RCD buffer and separate data buffers. It is a foundational building block for a wide range of OMI memory applications, including Differential Dual-Inline Memory Module (DDIMM) applications such as standard-height 1U DDIMMs with capacities from 16 GB to 128 GB and double-height 2U DDIMMs with capacities beyond 256 GB. It also supports chip-down applications to off-the-shelf Registered DIMMs (RDIMM) and NVDIMM-N devices.
The SMC 1000 8x25G integrates an on-chip processor that performs control path and monitoring functions such as initialization, temperature monitoring and diagnostics. It supports manufacturing test operations of attached DRAM memory. Microchip’s Trusted Platform support, including hardware root-of-trust, ensures device and firmware authenticity and supports secure firmware updates.
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