DDR Termination Regulators

The MIC5162 is a dual regulator controller designed for high-speed bus termination. It provides a universal solution for bus termination regardless of input voltage, output voltage or load current.

• Tracking programmable output
• Wide bandwidth
• Logic-controlled enable input
• Tiny MSOP-10 package

The MIC5163 is a dual regulator controller designed for low-voltage memory termination. The MIC5163 can operate from an input voltage as low as 0.75V.

• 0.75 to 6V input supply voltage
• Memory termination for DDR3, GDDR3/4/5
• Tiny MSOP-10 package

The MIC5164 is a dual regulator controller designed for high-speed bus termination. It offers a low-cost JEDEC-compliant solution for terminating high-speed, low-voltage digital buses with a Power Good (PG) signal.

• DDR, DDR2, DDR3 memory termination
• Tiny MSOP-10 package

DDR termination regulators are an essential component to regulate power through DDR transmission lines. DDR termination regulators achieve power conservation by rapidly dropping or increasing current so that the output termination voltage (VTT) would be half of the supply voltage (VDDQ). This results in reduced power dissipation and higher efficiency. Key benefits of these devices include: 

• Output current range from 0.75A to 2.6A
• Power good option
• Very accurate VTT as high as ±5 mV
• Available in MSOP-10 and DFN packages
• High-speed bus termination

DDR termination regulators are necessary to save power while DDR memory is active. Today, DDR is becoming even faster and more effective in transferring data and this makes the systems powering the DDR memory more susceptible to frequent and inaccurate data transfer. A good DDR termination regulator closely tracks supplied voltage and quickly sinks or sources current to maintain a regulated transmission of power. This ultimately leads to a more efficient double-data-rate memory and an indispensable power solution for a variety of mobile and home devices.