FPGA Hardware Design

This design suite enables high productivity with comprehensive, easy-to-learn and easy-to-adopt development tools for our power-efficient FPGAs.  

The SmartHLS compiler raises the abstraction level for faster design and easier verification of our FPGAs, SoC FPGAs and rad-tolerant FPGAs. 

Accelerate your time to market with our extensive suite of proven, optimized and easy-to-use IP cores for our FPGAs.   

Pre-compiled simulation libraries provide accurate device models for faster, more reliable FPGA design verification and reduced simulation setup time.

This secure programming solution helps prevent the overbuilding of electronic systems, reducing the risk of significant revenue loss.

Our programming and debug tools allow verification and troubleshooting at the hardware level.

• Libero SoC Design Suite v11.10
• Libero IDE
• ModelSim ME
• ModelSim Pro ME
• Synplify Pro ME
• MATLAB and Simulink for FPGA Design