Our EEPROM-based CPLDs use PAL architectures and are well suited for applications that require instant-on, fast-parallel logic operations and deterministic timing such as power, reset and wake control, waveform generation, encoding, decoding, I/O expansion, fault management, safety interlock chain, and timing and phase generation.
The ATF15xxAS/ASL/ASV/ASVL CPLDs are pin-compatible supersets of the popular Altera MAX7000/3000 series devices. They range from 32 to 128 macrocells with propagation delays from 7.5 to 25 ns. They are available in standard and low-power versions and support 3.3V and 5V VCC.
Our proprietary low-power L devices use Input Transition Detection (ITD) to automatically switch to power-down (standby) mode when all of the input and I/O pins are in static logic states. This family of CPLDs also supports JTAG In-System Programming (ISP) and Boundary Scan Test (BST).
The ATF15xx family of CPLDs delivers enhanced functionality and flexibility without requiring any additional design effort. The Logic Doubling architecture allows you to implement double the latch functions per macrocell, enabling you to use a smaller device or providing spare room for revisions. This family of devices also offers the most powerful switch matrix and routing resources of any CPLD while also supporting multiple independent feedbacks, individual output enable, global clear, D/T/latch-configurable flip-flops, more global clock pins and a programmable pin keeper circuit for bus interfacing.
Converting an Altera MAX7000/3000 series design is easy with our free, push-button POF2JED software utility that generates an industry-standard ATF15xx JEDEC programming file from an Altera POF file. Visit our PLD Design Resources page for information about software and hardware tools for our SPLDs.
