SmartHLS™ compiler software raises the FPGA design abstraction from traditional hardware description languages to C/C++ software, enabling shorter design time, easier verification and faster time to market for designs using our FPGAs.
In the SmartHLS compiler software, you can implement your design in C++ software and verify the functionality with software tests. Next, the SmartHLS high-level synthesis software compiles the C++ program into functionality-equivalent Verilog hardware modules. SmartHLS software can run co-simulation with ModelSim to verify cycle-accurate hardware behavior and confirm that the hardware functionality matches the software. SmartLHS software can generate hardware IP cores that you can integrate into a larger system using SmartDesign. It can also run Libero® software synthesis on the generated Verilog to determine the FPGA area and fMAX.
We have integrated the SmartHLS compiler software into Libero SoC Design Suite versions 2022.3 and later.
Beginning with Libero SoC v2024.1, the SmartHLS Compiler is now included under the Libero software license, providing a more integrated and streamlined development experience.