- PIC MCUs
- AVR MCUs
- 8051 MCUs
- Angular Timer
- Configurable Logic Cell
- Cyclic Redundancy Check
- Complementary Waveform Generator
- Direct Memory Access
- Event System
- High Endurance Flash
- Math Accelerator
- Numerically Controlled Oscillator
- Peripheral Pin Select
- Pulse-Width Modulation
- Temperature Indicator
- Timer Peripheral
- Windowed Watch Dog Timer
- Intelligent Analog
- Input and Output Features
- Core Independent
- Functional Safety
- Development Tools
8-bit Development Tools
AVR DB Product Family
8-bit MCUs Designed for Demanding Analog Applications
The AVR DB family builds upon the low-power performance of the AVR® core with a world-class selection of Core Independent Peripherals (CIPs) and a fully loaded Intelligent Analog portfolio, giving you the freedom to design tomorrow’s solutions today. Featuring three on-chip operational amplifiers (op amps), this family is unparalleled in its signal conditioning capabilities. With its Multi-Voltage I/O (MVIO), the AVR DB is a perfect companion microcontroller (MCU) in complex designs with multiple power domains.
This family of MCUs leverages on-board CIPs and a 5V operation mode for increased noise immunity while also reducing system latency by making use of the powerful Event System and Configurable Custom Logic (CCL) peripherals. The AVR-DB family’s MVIO allows true level-shifted bi-directional communication with devices on a different power domain. You can use the AVR DB family for real-time control functions in industrial control, home appliance, automotive, Internet of Things (IoT) and other applications.
Functional Safety Ready for Safety-Critical Applications
The AVR-DB family is recommended for safety-critical applications targeting both industrial and automotive products (IEC 61508 and ISO 26262). We also offer the MPLAB XC8 Functional Safety Compiler License, which is a TÜV SÜD certified compiler package that supports 8-bit PIC® and AVR microcontrollers. Documents such as FMEDA reports and safety manuals are available on request. Please contact your local Microchip sales office or your distributor for more information.
Built-in Level Shifters Add Flexibility and Reduce Cost
The AVR DB family of MCUs features a dedicated port for simultaneous multi-voltage operation, allowing this device to handle challenges on multiple power domains without needing external components. This port supports 1.8V–5.5V natively, allowing you to reduce cost and board space.
All-in-One Analog Signal Conditioning
The AVR DB also contains three highly configurable op amps that can be used individually or linked together to form gain stages for advanced analog signal conditioning. The integrated feedback resistor ladder allows many configurations without the need for external components. Using external resistors and capacitors gives you the full freedom to implement the signal conditioning feedback you need for your specific application. These op amps are fully supported by MPLAB® Code Configurator (MCC) and MPLAB® Mindi™ Analog Simulator so you can easily hit the ground running with code development and simulation.
*This board is based on the 128 KB 48-pin AVR DB MCU. An evaluation kit with the 64-pin AVR DB is not available.
Speed Up Your Development with Our Free Configuration Tools
Our intuitive, web-based graphical configuration tools will significantly reduce your development time. Offering an easy-to-use interface, MPLAB Code Configurator (MCC) and Atmel START generate factory-validated C code to help you get quickly started with your design. MCC is fully integrated into MPLAB X IDE so you can quickly and easily select and configure peripherals for your project. With just a few clicks, Atmel START projects can be imported into MPLAB X and Atmel Studio IDEs and can be easily modified at any time.
Example projects are available in both Atmel START and GitHub and are a great starting point for embedded programmers. They will work out of the box but are also easily modified.
Building Blocks for Robust and Safe Real-Time Control and Interface Applications
The on-board 12-bit, 130 ksps differential Analog-to-Digital Converter (ADC) features selectable internal voltage references with minimal temperature drift. It can be used to improve noise suppression and accuracy for analog inputs its hardware averaging and oversampling. Its averaging and threshold detection enables the MCU to remain asleep for longer periods, significantly reducing power consumption. Using the Event System, the on-board Analog Comparator (AC) can be connected to trigger autonomous operation in other peripherals, which is ideal for real-time control and closed-loop operations. The output of the 10-bit Digital-to-Analog Converter (DAC) can either be sent to a pin or it can be used to generate an adjustable reference voltage for the AC.
The Analog Signal Conditioning (OPAMP) peripheral features three operational amplifiers (op amps). These op amps are implemented with a flexible connection scheme using analog multiplexers and resistor ladders. This allows a large number of analog signal conditioning configurations to be achieved, many of which require no external components.
The Multi Voltage I/O (MVIO) system powers Port C and allows it to operate at a different voltage than the rest of the device. This greatly simplifies communication with other devices that might be running at a different voltage without the need of expensive external level shifters. If voltage is dropped on the VDDIO2 pin, an interrupt can be issued notifying the main application that the MVIO system is currently unpowered and not able to operate. If you do not want to use MVIO, VDDIO2 should be connected to VDD.
The Zero Cross Detect module can monitor AC line voltage and indicate zero crossing activity. This information is made directly available to the on-board Waveform Generation peripherals for use in TRIAC control applications, greatly reducing both Central Processing Unit (CPU) demand and overall development cost by lowering the bill of materials.
The Configurable Custom Logic (CCL) is a programmable logic peripheral that can be connected to the device pins, events or other internal peripherals. Each Lookup Table (LUT) consists of three inputs: a truth table, an optional synchronizer and a filter and edge detector. An LUT can generate an output to be routed internally or to an I/O pin, which eliminates the need for external logic and reduces BOM cost.
The Event System allows peripherals to communicate directly with each other without involving the CPU or bus resources. The Event System’s network is independent of the traditional data bus paths. This means that different triggers at the peripheral level can result in an event, such as a timer’s interrupts triggering an action in another peripheral. The Event System has three independent channels for direct peripheral-to-peripheral signaling. This deterministic signaling method is a perfect fit for real-time applications. The events are handled at the peripheral level even if the CPU is occupied handling interrupts or in sleep mode.
You can use the built-in features that support safety-critical applications to add robustness and reliability to your design. These include the Windowed Watchdog Timer (WDT) for system supervision, the Cyclic Redundancy Check (CRC) for scanning Flash memory, and the Event System for fault detection. Other features include a Voltage Level Monitor (VLM), a Brown-Out Detector (BOD) and Power-On Reset (POR) for monitoring the supply voltage.
The Cyclic Redundancy Check (CRC) is used to verify that there is no corruption in the application code. It calculates the checksum of the entire Flash memory, or parts of it, and automatically compares it with the expected result. This enables it to quickly and efficiently detect errors in program memory. The CRC can scan at run time or it can run during reset to ensure that the Flash memory is valid before the CPU is allowed to execute the code. When it is done at run time, the CRC scan temporarily halts the CPU to quickly complete the scan.
The Clock Failure Detect (CFD) is a system supervisory circuit that will switch over to the internal clock if the external crystal fails (stops). This additional safety level allows the device to run on a very precise clock. If the crystal fails, the device automatically switches to a secondary internal clock source and generates an interrupt to notify the main application that the external crystal has stopped. The user can then determine if the application needs to stop or go into a safe mode.
Safe startup of every device is essential. The Power-on Reset (POR) peripheral is used to generate a reset signal when a device is powered up to put it in a known state. It is also important that the device’s memories and digital logic have sufficient supply voltage to operate correctly. When the voltage rises, the POR is activated and will hold the device in reset until the voltage is above a fixed threshold value. The POR will remain enabled for as long as the device is powered.
AVR DB Key Attributes
- Internal 24 MHz oscillator
- Up to 128 KB of Flash memory
- Up to 16 KB SRAM
- Up to 22-channel, 130 ksps 12-bit differential Analog-to-Digital Converter (ADC)
- 10-bit 350 ksps Digital-to-Analog Converter (DAC)
- Analog signal conditioning (OPAMP)
- Analog Comparator (AC) with scalable reference input
- Up to three Zero-Cross Detectors (ZCDs)
- Cyclic Redundancy Check (CRC) scan
- Clock Failure Detect
- 16-bit Real Time Clock (RTC) and periodic interrupt timer
- Configurable Custom Logic (CCL) peripheral
- Up to 10-channel Event System peripheral
- Configurable, internally generated reference voltage
- USART/SPI/dual-mode Two-Wire Interface (TWI)
- Multi-voltage I/O on Port C
- 1.8V tolerant inputs selectable for all input pins
- Available packages:
- 64-pin TQFP/VQFN
- 48-pin TQFP/VQFN
- 32-pin TQFP/VQFN
- 28-pin SOIC/SSOP/SPDIP