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SY100EL34

Status: In Production

Features:

  • 3.3V and 5V power supply options
  • 50ps output-to-output skew
  • Synchronous enable/disable
  • Master Reset for synchronization
  • Internal 75KΩ input pull-down resistors
  • Available in 16-pin SOIC package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.

The VBB output is designed to act as the switching reference for the input of the EL34/L under single-ended input conditions. As a result, this pin can only source/ sink up to 0.5mA of current.The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple EL34/Ls in a system.

Additional Features
    • 3.3V and 5V power supply options
    • 50ps output-to-output skew
    • Synchronous enable/disable
    • Master Reset for synchronization
    • Internal 75KΩ input pull-down resistors
    • Available in 16-pin SOIC package
Parametrics
Name
Value
Product Type
Divider
Description
÷2, ÷4, ÷8 clock generation
Input
ECL/PECL
Supply Voltage
5
Max Prop Delay (ps)
1200
Max Within Device Skew (ps)
50
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
ECL/PECL

Documents

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY100EL34LZG
0.157400
0.300000
16
SOIC
.150in
Matte Tin
e3
SY100EL34LZG-TR
0.157400
0.307692
16
SOIC
.150in
Matte Tin
e3
SY100EL34ZG
0.157400
0.300000
16
SOIC
.150in
Matte Tin
e3
SY100EL34ZG-TR
0.157400
0.307692
16
SOIC
.150in
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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