FPGA News
PolarFire® FPGA Ethernet Sensor Bridge Rev 2.0 Expands Edge AI Connectivity
The new PolarFire FPGA Ethernet Sensor Bridge Rev 2.0 provides a smaller, more scalable platform for connecting high-speed image sensors to NVIDIA® edge AI systems. The updated platform is 60% smaller than the first generation, supports up to four MIPI CSI-2® cameras, adds NVIDIA Jetson™ camera connector compatibility and incorporates on-board optical latency measurement circuitry.
TechBytes Newsletter: July 2026 Edition
The July 2026 edition of FPGA and SoC TechBytes is now available, with new technical insights and application examples, including: VectorBlox™ Accelerator SDK 3.0 model optimization and compression; a DDR-free, Zephyr®-first PolarFire® SoC architecture; new SDI, HDMI®, DisplayPort™ and video-processing IP capabilities; hardware-based clock-glitch detection and configurable tamper response; and new medical imaging and space-system examples.
VectorBlox™ 3.0 Makes Edge AI More Efficient on PolarFire® FPGAs and SoCs
The new VectorBlox™ Accelerator SDK 3.0 makes it easier to deploy efficient AI inference on PolarFire® FPGA and SoC FPGA platforms. VectorBlox 3.0 adds support for sparse neural networks and advanced model compression, allowing the accelerator to skip unnecessary zero-valued operations and reduce compute, memory and bandwidth requirements.
The integrated tool flow supports familiar AI frameworks and provides model optimization, compilation, simulation and deployment capabilities, helping developers increase inference performance while maintaining the low power, security and reliability advantages of PolarFire devices. VectorBlox 3.0 can deliver up to 2× more AI performance using the same FPGA resources for supported sparse workloads.
Coming Soon—PolarFire® 2 FPGAs: Advancing Compute and Power Efficiency
Building on the proven power and thermal efficiency of today’s PolarFire® FPGA and PolarFire SoC FPGA families, PolarFire 2 FPGAs will deliver significantly greater compute capability while maintaining a strong focus on power efficiency. A new development toolset will also simplify FPGA acceleration, making it easier for algorithm and application developers to take advantage of FPGA performance without requiring deep FPGA design expertise.
