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SY898533L

Status: In Production

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Device Overview

Summary

The SY898533L is a 3.3V, low skew, 1:4 LVPECL fanout buffer with two selectable clock input pairs. Most standard differential input levels can be applied to the CLK, /CLK pair while LVPECL, CML, or SSTL input levels can be applied to the PCLK, /PCLK pair. To eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin, the clock enable is synchronized with the input signal.The SY898533L operates from a 3.3V ±5% supply and is guaranteed over the full industrial temperature range of 0°C to +70°C. The SY898533L is part of Micrel's highspeed, Precision Edge® product line.

Additional Features
  • Provides four differential 3.3V LVPECL copies
  • Selects between differential CLK, /CLK or LVPECL clock inputs
  • CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL input levels
  • PCLK, /PCLK pair accepts LVPECL, CML, SSTL input levels
  • 650MHz Maximum output frequency
  • <1.4ns Propagation delay (In-to-Q)
  • <30ps Output skew
  • <150ps Part-to-part skew
  • 3.3V ±5% supply voltage
  • 0°C to +70°C temperature operating range
  • Available in a 20-pin TSSOP package
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Description
2:4
Input
Multiple
Output
LVPECL
Supply Voltage
3.3
Max Freq (GHz)
0.65
Max Prop Delay (ps)
1400
Icc (mA)
50
Max Within Device Skew (ps)
30
OE
False
RPE
False
FSI
False
Input Mux
True
Input EQ
False
Output Type
LVPECL

Documents

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Data Sheets

  
1034KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY898533LKZ-TR
0.078000
0.200000
20
TSSOP
4.4mm
Matte Tin
e3
SY898533LKZ
0.078000
0.175676
20
TSSOP
4.4mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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