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SY89251V

Status: In Production

Features:

  • 3.3V and 5V power supply options
  • 250ps propagation delay
  • Ideal for pulse amplifier and limiting amplifier applications
  • Data synchronous enable/disable (EN) on QHG and /QHG provides for complete glitchless gating of the outputs
  • Ideal for gating timing signals
  • Complete solution for high quality, high frequency crystal oscillator applications
  • Available in an ultra-small 8-pin (2mm x 2mm) DFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY89251V is a differential PECL/ECL receiver/buffer in a space saving (2mm x 2mm) DFN package. The device is functionally equivalent to the SY100EL16VC, except for an active HIGH enable pin and a 70% smaller footprint. It is also equivalent to the SY89250V, except for an active HIGH enable pin. It provides a VBB output for either single-ended application or as a DC bias for AC-coupling to the device.The SY89251V provides an EN input which is synchronized with the data input (D) signal in a way that provides glitchless gating of the QHG and /QHG outputs.

When the EN signal is HIGH, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and the EN goes LOW, it will force the QHG LOW and the /QHG HIGH on the next negative transition of the data input. If the data input is LOW when the EN goes LOW, the next data transition to a HIGH is ignored and QHG remains LOW and /QHG remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and /QHG outputs remain in their disabled state as long as the EN input is held LOW. The EN input has no influence on the /Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal for crystal oscillator applications, where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.

Additional Features
    • 3.3V and 5V power supply options
    • 250ps propagation delay
    • Ideal for pulse amplifier and limiting amplifier applications
    • Data synchronous enable/disable (EN) on QHG and /QHG provides for complete glitchless gating of the outputs
    • Ideal for gating timing signals
    • Complete solution for high quality, high frequency crystal oscillator applications
    • Available in an ultra-small 8-pin (2mm x 2mm) DFN package
Parametrics
Name
Value
Product Type
Receiver
Description
Equivalent to SY100EL16VC
Input
ECL/LVPECL
Output
ECL/LVPECL
Supply Voltage
3.3/5V
Max Prop Delay (ps)
380
Icc (mA)
26
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Channels
Single
Output Type
ECL/LVPECL

Documents

Jump to:

Data Sheet

11/11/2015
178KB

User Guides

11/11/2015
301KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89251VMG-TR
0.010900
0.339227
8
VDFN
2x2x0.9mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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