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SY100EL92

Status: In Production

Features:

  • 5V and 3.3V power supplies required
  • Also, supports LVPECL-to-PECL translation
  • 500ps propagation delays
  • Fully differential design
  • Differential line receiver capability
  • Application note
  • Available in 20-pin SOIC package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY100EL92 is a triple LVPECL-to-PECL or PECLto-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). SY100EL92 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals. However, please note that for the latter we will need two different power supplies. Please refer to Function Table for more details.VBB outputs are provided for interfacing single ended input signals. If a single ended input is to be used, the VBB output should be connected to the D input and the active signal will drive the D input. When used, the VBB should be bypassed to VCC via a 0.01µF capacitor.

The VBB is designed to act as a switching reference for the SY100EL92 under single ended input conditions. As a result, the pin can only source/sink 0.5mA of current.To accomplish the PECL-to-LVPECL level translation, the SY100EL92 requires three power rails. The VCC and VCC_VBB supply is to be connected to the standard PECL supply, the 3.3V supply is to be connected to the VCCOsupply, and GND is connected to the system ground plane.

Both the VCC and VCCO should be bypassed to ground with a 0.01µF capacitor.To accomplish the LVPECL-to-PECL level translation, the SY100EL92 requires three power rails as well. The 5.0V supply is connected to the VCC and VCCO pins, 3.3V supply is connected to the VCC_VBB pin and GND is connected to the system ground plane. VCC_VBB is used to provide a proper VBB output level if a single ended input is used. For differential LVPECL input VCC_VBB can be either 3.3V or 5V.Under open input conditions, the D input will be biased at a VCC/2 voltage level and the D input will be pulled to GND. This condition will force the "Q" output low, ensuring stability.

Additional Features
    • 5V and 3.3V power supplies required
    • Also, supports LVPECL-to-PECL translation
    • 500ps propagation delays
    • Fully differential design
    • Differential line receiver capability
    • Application note
    • Available in 20-pin SOIC package
Parametrics
Name
Value
Product Type
Logic Translators
Input
PECL/LVPECL
Output
PECL/LVPECL
Supply Voltage
3.3/ 5/-5
Max Freq (GHz)
0.3
Max Prop Delay (ps)
630
Icc (mA)
12
Max Within Device Skew (ps)
100
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Channels
Triple
Output Type
PECL/LVPECL
Output Voltage
3.3/5/-5

Documents

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY100EL92ZG-TR
0.540800
1.461700
20
SOIC
.300in
NiPdAu
e4
SY100EL92ZG
0.540800
1.086316
20
SOIC
.300in
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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