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SST39LF802C

8Mb 3-3.6V Parallel Flash

Status: In Production

Features:

  • Organized as 512K x16
  • Low Power Consumption (typical values at 5 MHz)– Active Current: 5 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
  • Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 8 KWord)– Bottom Block-Protection (bottom 8 KWord)
  • Sector-Erase Capability– Uniform 2 KWord sectors
  • Block-Erase Capability– Flexible block architecture; one 8-, two 4-, one16-, and fifteen 32-KWord blocks
  • Chip-Erase Capability
  • Erase-Suspend/Erase-Resume Capabilities
  • Hardware Reset Pin (RST#)
  • Latched Address and Data
  • Security-ID Feature– SST: 128 bits; User: 128 words
  • Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
  • Automatic Write Timing– Internal VPP Generation
  • End-of-Write Detection– Toggle Bits– Data# Polling– Ready/Busy# Pin
  • CMOS I/O Compatibility
  • JEDEC Standard– Flash EEPROM Pinouts and command sets
  • Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (6mm x 8mm)- 48-ball WFBGA (4mm x 6mm)
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Overview
Documents
Development Environment
Similar Devices
RoHS Information
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Device Overview

Summary

The SST39LF802C device is 512K x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF802C writes (Program or Erase) with a 3.0-3.6V power supply. This device conforms to JEDEC standard pinouts for x16 memories.

Additional Features
    • Organized as 512K x16
    • Low Power Consumption (typical values at 5 MHz)– Active Current: 5 mA (typical)– Standby Current: 3 µA (typical)– Auto Low Power Mode: 3 µA (typical)
    • Hardware Block-Protection/WP# Input Pin– Top Block-Protection (top 8 KWord)– Bottom Block-Protection (bottom 8 KWord)
    • Sector-Erase Capability– Uniform 2 KWord sectors
    • Block-Erase Capability– Flexible block architecture; one 8-, two 4-, one16-, and fifteen 32-KWord blocks
    • Chip-Erase Capability
    • Erase-Suspend/Erase-Resume Capabilities
    • Hardware Reset Pin (RST#)
    • Latched Address and Data
    • Security-ID Feature– SST: 128 bits; User: 128 words
    • Fast Erase and Word-Program:– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Chip-Erase Time: 40 ms (typical)– Word-Program Time: 7 µs (typical)
    • Automatic Write Timing– Internal VPP Generation
    • End-of-Write Detection– Toggle Bits– Data# Polling– Ready/Busy# Pin
    • CMOS I/O Compatibility
    • JEDEC Standard– Flash EEPROM Pinouts and command sets
    • Packages Available– 48-lead TSOP (12mm x 20mm)– 48-ball TFBGA (6mm x 8mm)- 48-ball WFBGA (4mm x 6mm)
Parametrics
Name
Value
Density
8 Mbit
Op. Volt Range (V)
3 to 3.6
Read Access Time
55 ns
Temp Range (°C)
0°C to +70°C
Endurance
100,000
Data Retention (Years)
100

Documents

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Brochures

12/19/2017
3698KB

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Product
Memory Size
Memory Speed
Package
Price 5K
 
0 kHz
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$1.25
 
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$0.75
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0 MHz
TFBGA-48, TSOP-48, WFBGA-48
$0.75
 
0 kHz
TFBGA-48, TSOP-48, WFBGA-48
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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SST39LF802C-55-4C-B3KE
0.094100
0.666667
48
TFBGA
6x8x1.2mm
SAC
e1
SST39LF802C-55-4C-B3KE-T
0.094100
0.336000
48
TFBGA
6x8x1.2mm
SAC
e1
SST39LF802C-55-4C-MAQE
0.028700
0.459460
48
WFBGA
4x6x0.73mm
SAC
e1
SST39LF802C-55-4C-MAQE-T
0.028700
0.240800
48
WFBGA
4x6x0.73mm
SAC
e1
SST39LF802C-55-4C-EKE
0.564500
2.770833
48
TSOP
12x20mm
Matte Tin
e3
SST39LF802C-55-4C-EKE-T
0.564500
0.940000
48
TSOP
12x20mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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