The Universal Timer (UTMR) peripheral combines most of the operations of the legacy timers (TMR0/1/2, HLT, SMT, CCP) into a single timer. This means useful features such as periodic operation mode, clock gating, pulse width measurement and switch debouncing are combined into one feature-rich module.
Multiple UTMR modules can be chained together to form larger-sized timers, providing system design flexibility.
Timer 0 is the simplest timer available for PIC devices. It can operate as either a 16-bit or 8-bit timer or counter. This peripheral can operate in low-power sleep modes provided that the internal or external clock source remains active. It also has a programmable prescaler, postscaler and period and can operate in a variety of modes.
In timer mode, a timer variable will increment on every instruction cycle as long as there is a valid clock input signal. This mode can operate both synchronously and asynchronously with an external clock signal. Timer mode can also perform in lower-power sleep modes only if operating asynchronously from the system clock.
In counter mode, the clock input the counter increments by one on each rising edge. This mode can operate both synchronously and asynchronously as well. However, just like the timer mode, this mode can only operate if working asynchronously from the system clock.
Timer 1,3,5… (odd-numbered timers) all behave in the same manner. This enables a device to control multiple timer peripherals with different operating behaviors if desired. These timers can operate as 16-bit timers or counters, and they have programmable prescalers. They can also operate in low-power sleep modes provided that the internal or external clock source remains active. The odd-numbered timers are unique in their ability to enable and disable gate modes, which allows you to set your timer or counter to only increment under certain conditions based on the required Gate Signal Source.
When Gate Enable mode is active, the timer will begin incrementing on the rising edge of the gate input source. It will increment on every rising edge of the timer’s clock source. On the falling edge of the timer’s gate input source, the timer will stop incrementing.
When Toggle Mode is enabled, the duration between each toggling of the gate input signal can be measured. The timer will begin incrementing on the rising edge of the Gate Signal Source. It will continue to increment until the next rising edge of the gate signal source occurs. You can use this to read the entire toggle period of your Gate Signal Source.
When Single Pulse Mode is enabled, the timer counter will begin incrementing on the rising edge of the incoming Gate Signal Source. The timer will continue to increment until the falling edge of the Gate Signal Source occurs. This enables you to read the duration of the high pulse of the incoming Gate Signal Source.
These two operating modes can be used simultaneously. This allows both the high pulse duration and the period to be obtained at the same time, which can be converted into duty cycle if so desired.
Timer 2,4,6… (even-numbered timers) are duplicates of one another. The even-number timer peripherals are 8-bit timers with the ability to be reset by an external hardware source or an internal timer period match. These timers cannot operate in lower-power sleep modes. The even-numbered timers compare a predefined period value to an incrementing timer counter. When the two values match an output postscaler counter is incremented and a subsequent action can be triggered. This timer also features multiple operating modes.
In Free Running Mode, the timer counter is reset each time a period match occurs. As long as the timer is enabled, it will continue to increment until a period match occurs and it resets. An external hardware signal can reset the timer before a period match occurs if desired.
In One Shot Mode, the timer value increments until a period match occurs, after which the timer will stop and remain halted until it is restarted. An external hardware signal can be used to reset the timer.
In Monostable Mode, the timer value increments until a period match occurs, after which the timer is stopped but is not disabled. An external hardware signal can be used to reset the timer.
The signal measurement timer can be found on newer PIC devices and can be used for measuring different signal parameters such as pulse width, frequency, duty cycle and the time difference between edges on two signals. It can work as a 16-bit or 24-bit timer, and it has a combination of attributes and operating modes that are present on other PIC MCU timers.
In Timer Mode On, the signal measurement timer works similarly to Timer Mode on Timer0. As long as there is a valid clock input signal, a timer variable will increment on every instruction cycle.
In Gated Timer Mode, the timer will only increment while the incoming Gate Signal is high. When it is low, the timer will stop incrementing. As a result, the signal measurement timer will only increment under specific conditions.
In Period and Duty Cycle Mode, either the duty cycle or period of the incoming signal to the Signal Measurement Timer can be acquired. They cannot both be measured simultaneously.
In High and Low Measurement Mode, the high and low pulse time of the incoming signal can be acquired.
In Gated Windowed Measurement Mode, the duty cycle of the Signal Measurement Timer signal input over a user-defined window or period can be acquired.
Time of Flight Mode measures the time between the rising edge of the Signal Measurement Timer signal input and the rising edge of the Signal Measurement Timer window input.
In Capture Mode, the value of the timer is captured based on the rising or falling edge of the Signal Measurement Window input and triggers an interrupt.
Gated Counter Mode counts pulses on the SMT input signal which is gated by the SMT window input. The timer only increments after the rising edge of the SMT window input. It stops counting on the falling edge.
Windowed Counter Mode counts the amount pulses of an input signal and the duration of the signal’s high pulse within a defined window. To measure the duration of the high pulse, the SMT begins counting on the rising edge of an input signal and stops counting on the falling edge. To count the number of pulses of an input signal, a counter value is incremented on each rising edge of the windowed signal.
Timers on AVR MCUs are designed a little differently than the timers on PIC MCUs. The biggest difference is that the timers on AVR MCUs are integrated with waveform output modules like the Pulse-Width Modulation (PWM) and Complimentary Waveform Generator (CWG), while PIC MCUs have separate peripherals for these functions.
Timer/Counter 0, 1, 2, etc., on AVR devices are basic timers. Not only do they perform as a basic timer or counter, they also have some intelligent features.
The basic timers can directly output a PWM signal with variable duty cycles and period. Fast PWM mode is used for generating high-frequency PWM, while Phase and Frequency Correct PWM is used for generating high-resolution PWM.
The timer compares a user-defined value with the counter value in the timer. When the timer is running, the counter value will keep increasing until it meets the user-defined value. The timer counter is then automatically cleared, or an interrupt can be generated to notify the user. This feature can be used when you need to trigger or output an event at a specific time.
Some basic timers can capture internal/external events, such as a rising edge of an external signal, and give them a time stamp indicating the time of occurrence. The timestamps can then be used to calculate the features of the signal such as frequency or duty cycle. There is also an option to enable a noise canceler to improve noise immunity to the captured signal.
Timer/Counter Type A, or TCA, is available in most new AVR MCUs. It is a 16-bit timer that can perform basic timing/counting, output compare and different types of PWM waveform generation.
TCA has three compare channels and, similar to the basic timers, it performs the output compare function. You can load three different values into the three compare registers to trigger three events or interrupts as the timer counter increments. This allows you to trigger multiple events at different times.
There are two kinds of common PWMs: edge-aligned or center-aligned. The edge-aligned PWM is widely used because of its simple configuration and higher resolution. The center-aligned PWM is extremely helpful in reducing the harmonics in the output of applications like motor control or power supply. TCA has can generate a high-resolution PWM with either a Single-Slope Mode or a Dual-Slope Mode. The Single-Slope Mode generates a left-aligned PWM, which has the high state at the beginning of a PWM period. The Dual-Slope Mode generates a center-aligned (symmetric) PWM, which has the high state at the middle of a PWM period.
TCA has a Split Mode, which splits the timer/counter into two timers with half the resolution. These two timers can perform basic functions such as counting and timing, single-slope PWM output and generating interrupts.
Timer/Counter Type B, or TCB, is available in most new AVR MCUs. It is a high-resolution timer that can perform basic timing/counting, input/event capture, waveform measurement and PWM waveform generation.
TCB can capture internal/external events, such as a rising edge of an external signal, and give them a timestamp indicating the time of occurrence. There is also an option to enable a noise canceler to improve noise immunity to the captured signal.
The Input Capture module of TCB also contains frequency and pulse-width measurement modes. Three modes allow you to measure frequency, pulse width, or both at the same time. These modes allow you to measure a periodic signal coming from another device or source. For example, you can use these modes to determine the period and duty cycle of a PWM signal so it can be used as an input feedback for the control system.
This mode can be used to generate a pulse with a duration every time a rising or a falling edge occurs on the input event. The timer will start counting when it detects the first rising/falling edge and counts to a user-defined counter value. This feature is useful for generating a fixed duration of event/output based on either a periodic or a non-periodic input.
Timer/Counter Type D, or TCD, is available in some new AVR MCUs. It is a 12-bit timer with some specific features for complex waveform generation. It also contains flexible input capture and compare modes. This timer is extremely useful for timing- or safety-critical applications that require fault detection and for driving the output for a power supply or a motor.
TCD has two input channels with ten modes of capturing input. Based on the mode you select, different actions/waveforms can be generated when there is an input, such as shutting down the output waveform or giving a flag to the microcontroller to perform additional operations in software. Additional signal processing features, such as input signal blanking and filtering, can be applied to the modes.
Like TCA, TCD can also generate center-aligned PWM by using a Dual-Slope Mode. It is very useful for applications like power converters or motors. It can also generate edge-aligned PWMs with conditional timings based on the user-selected input capture mode.
TCD can also generate signals for full-bridge and half-bridge output. The complimentary signals and dead time are generated automatically. Full-bridge and half-bridge are commonly used in driving power supply and motors. This eliminates the need to configure the output using software, which reduces the overhead for the CPU. It also eliminates the need to add external hardware logic components, which reduces costs.
The Hardware Limit Timer (HLT) provides a timed hardware limit to be used in conjunction with asynchronous analog feedback applications, or to detect missed periodic events.
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