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IP Core
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Versatile AES256

Versatile AES256 is a balanced and a versatile Intellectual Property (IP) core implementing the Advanced Encryption Standard (AES) with a 256-bit key in five dynamically selectable modes of operation: Electronic Codebook (ECB), Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB), and Counter (CTR). The four different modes of operation (CBC, CFB, OFB, and CTR) all protect data confidentiality, and are widely used in numerous security designs and cryptographic protocols. It also supports the ECB mode of operation as a building block for other AES modes of operation, but importantly the standalone use of ECB is not recommended for cryptographically secure applications. The design  allows every individual 128-bit data block (din —plaintext in encryption mode, ciphertext in decryption mode) to use a different key, a different Initialization Vector (IV) , and a different mode of operation.


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Features and Benefits

  • Optimized resource requirements: 
    • Requires 4051 4-input Lookup Tables (4LUTs) for Microchip® PolarFire® . 
    • Does not require any multipliers, DSPBlocks or internal memory in a typical Microchip® FPGA implementation. 
  • Performance: 
    • Achieves a high throughput up to 100s of Gbps compliant with NIST Standards.
    • The key, initialization vector (IV), and the mode of operation can be dynamically updated for every 128-bit data clock. 
  • Standard Compliance: 
    • Fully compliant with both the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard. 
    • NIST support for various AES modes including GCM, CTR, XTS, ECB, CBC, CFB, and OFB.
  • Easy Integration : 
    • Pure RTL without hidden CPU or software components. 
    • Vendor agnostics FPGA/ASIC implementation. 

Licensing Options

For additional information contact: sales@xiphera.com or visit Xiphera 

Documentation

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