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IP Core
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I3C-T

The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & compliant with the latest MIPI I3C BasicSM specification. The highly featured target-only core communicates in Single Data Rate (SDR) mode, but can tolerate High Data Rate (HDR) traffic. It can coexist and communicate with legacy I2C devices, and it can optionally be configured to operate as such in an I3C or I2C bus. The I3C-T needs no firmware support to parse and execute the broadcast or direct Common Command Codes (CCCs) relevant to I3C Basic Targets.


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Features and Benefits

  • Basic Protocol :
    • Supports up to 12.5 Mbit/s in SDR (Single Data Rate) mode and is HDR-tolerant (High Data Rate) as a target.
    • Handles all relevant Broadcast and Direct Common Command Codes (CCCs) autonomously.
    • Implements the Hot-Join mechanism.
    • Uses In-Band Interrupts.
    • Manages I3C Bus and Device Characteristic Registers (BCR & DCR).
    • Supports Dynamic Addressing Assignment.
  • I2C Interoperability :
    • Can operate as a legacy I2C device.
    • Is interoperable with legacy I2C devices.
    • Supports I2C static addressing and messaging.
    • Includes a 50ns spike filter.
  • Ease of Use & Integration :
    • Offers run-time selectable operational modes:
      • Autonomous I3C-to-AHB bridge.
      • Firmware-assisted mode for data exchange via APB-accessible registers or custom protocol implementation.
    • Uses standardized AMBA interfaces:
      • APB-Subordinate for register access.
      • AHB-Manager for I3C-to-AHB bridging mode.
      • Features independent clocks for APB, AHB, and I2C with clean clock domain crossing.
      • Fully synchronous, scan-ready, and LINT-clean design.

Licensing Options

For additional information, contact info@cast-inc.com or visit CAST

Documentation

Title
i3c-si--mipi-i3c-basic-slave-controller-and-i3c-to-ahb-bridge Link