CoreEDAC is designed to enhance the reliability of memory systems within their FPGAs, specifically the SmartFusion2 and PolarFire families. Essentially, it's a configurable tool that generates the necessary logic to perform error detection and correction (EDAC). This is particularly crucial for applications in environments prone to radiation-induced memory errors, such as in aerospace, defense, and other safety-critical systems. The core offers flexible operation modes. It can be tightly integrated with the FPGA's on-chip RAM, creating a protected memory block, or it can generate standalone encoder and decoder blocks to secure external memory devices.
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Features and Benefits
- Modes of Operation :
- EDAC with internal RAM: Generates EDAC logic integrated with on-chip RAM.
- EDAC RAM generation with optional background scrubbing circuitry: Creates EDAC RAM with an optional feature to automatically correct single-bit errors in the background.
- EDAC encoder and decoder generation: Creates a standalone encoder and decoder, which can be used to apply EDAC to external memories.
- Parameterization and Configuration :
- It is a parameterizable RTL generator, allowing users to define specific parameters.
- User data size: Flexible, from 4 to 64 bits.
- Codeword size: Corresponds to the data size, ranging from 8 to 72 bits.
- Optional features: Includes the ability to suppress write-back during scrubbing and offers an option for triple EDAC redundancy..
- Key Benefits :
- Produces FPGA-optimized logic for error detection and correction.
- Helps increase the reliability of on-chip RAM and external memories.
Licensing Options
Free with any Libero License
Documentation
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| CoreEDAC User Guide | Download |