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SY10H842

3.3V Quad PECL-to-TTL with Latched Output Enable

Status: Not Recommended for new designs

Features:

  • Translates positive ECL-to-TTL (PECL-to-TTL)
  • 300ps pin-to-pin skew
  • 500ps part-to-part skew
  • Differential internal design for increased noise immunity and stable threshold inputs
  • VBB reference output
  • Single supply
  • Enable input
  • Extra TTL and ECL power/ground pins to reduce cross-talk/noise
  • High drive capability: 24mA each output
  • Fully compatible with industry standard 10K, 100K I/O levels
  • Available in 16-pin SOIC package
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Device Overview

Summary

The SY10/100H842 are single supply, low skew translating 1:4 clock drivers.The devices feature a 24mA TTL output stage, with AC performance specified into a 50pF load capacitance. A HIGH on the enable pin (EN) forces all outputs LOW. As frequencies increase to 40MHz and above, precise timing and shaping of clock signals becomes extremely important. The H842 solves several clock distribution problems such as minimizing skew 300ps), maximizing clock fanout (24mA drive), and precise duty cycle control through a proprietary differential internal design.The 10K version is compatible with 10KH ECL logic levels. The 100K version is compatible with 100K levels.

Additional Features
    • Translates positive ECL-to-TTL (PECL-to-TTL)
    • 300ps pin-to-pin skew
    • 500ps part-to-part skew
    • Differential internal design for increased noise immunity and stable threshold inputs
    • VBB reference output
    • Single supply
    • Enable input
    • Extra TTL and ECL power/ground pins to reduce cross-talk/noise
    • High drive capability: 24mA each output
    • Fully compatible with industry standard 10K, 100K I/O levels
    • Available in 16-pin SOIC package
Parametrics
Name
Value
Description
D Latch.
Supply Voltage
5V
Max Freq (GHz)
2.5
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
CML

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