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32-bit Low-Power Microprocessors

Sophisticated wearable technology, wireless sensor networks and other smart appliances that need to connect to the Internet of Things (IoT) require high-performance and power-efficient devices that also incorporate security features to protect these applications. To meet these requirements, our 32-bit Arm® Cortex®-A5 based microprocessors (MPUs) are designed to efficiently run on Linux® platforms and modern Graphical User Interfaces (GUIs) while conserving energy in sleep or back-up modes.

Benefits of 32-bit MPUs

Two Ultra-Low Power Sleep Modes

  • ULP0 Mode with configurable sleep current /wake-up settings from 250 μA/4.7 ms to 3.2 mA/13 μs; wake-up from any interrupt source
  • ULP1 Mode sleep current down to 300 μA with fast 15 μS, with wake up from restricted pin set
  • Patented SleepWalking feature enables peripherals to asynchronously wake up from sleep in ULP1 mode, for example, when triggered by activity on a communications line

High-Performance, Power-Efficient Arm Cortex-A5 Core

  • 500/536 MHz (’D2/’D3) CPU with Floating Point Unit (FPU)
  • 140 mW (233 μA)/MHz operation
  • Arm Neon™ technology improves DSP operations (’D2)
    • – 1.32V VDD core
  • 32 KB L1 data/instruction caches
  • 128 KB L2 cache (’D2)
  • 128 KB on-chip SRAM
  • LPDDR1/LPDDR2 support and LPDDR3L support (’D2)

Back-Up Mode Enables Battery Operation

  • VDDBU pin for battery domain with low 4.5 μA backup current (typ.)
  • Real Time Clock (RTC) with alarm and security module remain active
  • 5 KB SRAM data and 256-bit register file save application context
  • Optional DDR Self-Refresh Mode maintains external SDRAM contents for faster recovery (40 μA)
  • Wake up from RTC alarm, 10 wake-up pins, analog comparator or LP UART RX character input

Comprehensive Peripheral Set and High-Grade Security Features

  • SDIO/SD/eMMC, QSPI, Hi-Speed USB, 10/100 and Gigabit Ethernet (‘D3), Flexcoms, CAN FD, 12-bit Analog to Digital Converters (ADCs), timers, 24-bit TFT LCD controller with overlays, resistive touch, capacitive touch (’D2), an audio subsystem with PLL, I2S™, SSC/TDM channels, a class D amplifier and digital microphone (’D2)
  • Arm TrustZone® technology, crypto engine, unique on-the-fly encryption and decryption of software code from the external DRAM and QSPI, secure boot, tamper detection pins, safe erasure of security-critical data, voltage and frequency monitoring, and a unique ID in each device provide exceptional data security (’D2)

32-bit Low-Power MPU Product Specifications

Device FamilyCore FPU/Neon™/TrustZone®Clock
Speed (MHz)
SRAM (KB)L1 Cache
I and D
L2 Cache (KB)QSPI
and Gigabit
SAMA5D2Arm Cortex®-
A5 Core
Y/Y/Y5001282x321282Y/NHigh-grade security, up to two SD/SDIO/eMMC, up to two CAN FD, two Hi-Speed USB, one HSCI, 24-bit TFT-LCD controller with overlays, camera interface, audio subsystem, capacitive touch controller
SAMA5D3Arm Cortex-
A5 Core

Up to three SD/SDIO/eMMC, up to two CAN FD, three Hi-Speed USB, 24-bit TFT-LCD controller with overlays, camera interface, resistive touch controller