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32-bit Microprocessors (MPUs)

As more sophisticated wearable technology, wireless sensor networks and other smart appliances are connected to the Internet of Things (IoT), the need for higher performance devices that can conserve energy and securely protect the application are required.  Microchip MPUs fill this need with Cortex®-A5 based ARM cores designed to efficiently run Linux and modern GUIs and still sip energy in sleep or back-up modes.

Benefits of 32-bit MPUs

Two Ultra Low Power Sleep Modes

  • ULP0 Mode with configurable sleep current /wake-up settings from 250μA/4.7ms to 3.2mA/13μs; wake-up from any interrupt source
  • ULP1 Mode sleep current down to 300μA with fast 15μS, with wake-up from restricted pin set
  • Patented SleepWalking feature enables peripherals to asynchronously wake-up from sleep in ULP1 mode, e.g. by activity on a communications line

High performance, power efficient ARM Cortex-A5 MPU core

  • 500/536 MHz (‘D2/’D3) CPU with Floating Point Unit (FPU)
  • 140mW (233μA)/MHz operation
  • ARM NEON engine improves DSP operations (‘D2)
  • 1.1 – 1.32v Vddcore
  • 32KB L1 Data/Instruction Caches
  • 128KB L2 Cache (‘D2)
  • 128KB on-chip SRAM
  • LPDDR1/LPDDR2 support and LPDDR3L support (‘D2)
 

Back-Up Mode enables battery operation

  • Vddbu pin for battery domain with low 4.5μA back-up current (typ.)
  • RTC with alarm and Security Module remain active
  • 5KB SRAM data and 256-bit register file save application context
  • Optional DDR Self-Refresh Mode maintains external SDRAM contents for faster recovery (40μA)
  • Wake-up from RTC alarm, 10 wake-up pins, analog comparator or LP UART RX character input

Comprehensive peripheral set and high-grade security features

  • SDIO/SD/eMMC, QSPI, HS-USB, 10/100 and Gb Ethernet (‘D3), Flexcoms, CAN-FD, 12-bit A/Ds, Timers, 24-bit TFT LCD Controller with overlays, Resistive Touch, Cap Touch (‘D2), an Audio subsystem with PLL, I2S, SSC/TDM channels, a class D amplifier and digital microphone (‘D2).
  • ARM TrustZone, crypto engine, unique on-the-fly encryption and decryption of software code from the external DRAM and QSPI, secure boot, tamper detection pins, safe erasure of security-critical data, voltage and frequency monitoring, and a unique ID in each device provide exceptional data security (‘D2).
 

32-bit Low-Power MPU Product Specification

Device Family Core FPU/NEON/TrustZone Clock Speed (MHz) SRAM (KB) L1 Cache I&D (KB) L2 Cache (KB) QSPI Inter-face 10/100 & Gbit Ethernet Highlights
SAMA5D2 Cortex-A5 Y/Y/Y 500 128 2x32 128 2 Y/N High-Grade Security, up to 2 SD/SDIO/eMMC, up to 2 CAN-FD, 2-HS-USB, 1 HSCI, 24-bit TFT-LCD Controller with overlays, Camera I/F, Audio Subsystem, Cap Touch Controller
SAMA5D3 Cortex-A5 Y/N/N 536 128 2x32     Y/Y Up to 3 SD/SDIO/eMMC, up to 2 CAN-FD, 3-HS-USB, 24-bit TFT-LCD Controller with overlays, Camera I/F, Resistive Touch Controller