Clock and Timing
Clock and Data Distribution
We offer one of the most extensive arrays of clock distribution product lines in the industry. Ranging from 2 to 22 outputs, they support differential (LVPECL, LVDS, HCSL, CML) and single-ended CMOS outputs, and have a maximum clock rate of 7.0 GHz and data rate of 10.7 Gbps, with very low additive jitter. Our clock distribution family consist of TCXO fanout buffers, crystal or reference input fanout buffers, signal translators, cross-point switches, high-performance clock dividers, receiver-buffer drivers, multiplexers, delay lines and logic gates.