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Use of the SSP Module in the IIC Multi-Master Environment
Scott Fink
The Inter-IC (I 2 C) bus is a two-wire serial interface developed by Philips/Signetics. The specification supports data transmission up to 400 Kbps. The I 2 C interface employs a comprehensive protocol to ensure reliable transmission and reception of data. When the bus is active, one device is the Master (generates the clock and the handshaking signals), while all the other devices are Slaves. The current bus Master can both read-from and write-to any of the Slave units by addressing them individually. On a Multi-Mas-ter bus the Masters follow an arbitration scheme to ensure that the bus is not corrupted. Each device attached to the I 2 C bus is assigned a unique address. When a Master wishes to initiate a data transfer, it first transmits the address of the device that it wishes to ?talk? to. All devices ?listen? to see if this is their address. Within this address, a bit specifies whether the Master wishes to read-from or write-to the Slave device. The output stages of each device on the bus, attached to the clock (SCL) and data (SDA) lines, must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no device is pulling the line down. The only limitation on the number of devices that may be attached to the bus is the maximum bus loading specification. For complete bus specifications, refer to Philips/Signetics document ?The I 2 C-bus and How to Use It? (www.semiconductors.philips.com).
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