CoreFPU

CoreFPU is a floating-point unit that adds hardware-based arithmetic and number format conversion to FPGA designs that need deterministic math processing. It is intended for systems where software execution of floating-point operations would consume processor bandwidth or complicate timing closure. The core supports arithmetic on normalized floating-point data and also bridges fixed-point and floating-point domains, which helps designers combine sensor, control, and algorithm pipelines within one architecture. Its top-level structure lets the design instantiate the specific operation needed, so logic is focused on the selected function instead of a broader math subsystem. This makes the core well suited for embedded compute paths that require predictable behavior, direct hardware handoff, and straightforward integration into larger signal-processing or control datapaths. Status reporting for exceptional results also helps downstream logic detect overflow, underflow, infinity, and NaN conditions without extra software intervention. With support for IEEE® 754 floating-point formats and a pipelined arithmetic implementation, CoreFPU fits applications that need reusable math acceleration in FPGA fabric, especially DSP and embedded processing systems that mix fixed-point interfaces with floating-point computation.