CoreCAN is a configurable Controller Area Network (CAN) IP core that implements the CAN 2.0A and CAN 2.0B protocols for reliable serial communication in embedded and industrial systems. The core supports both standard (11-bit) and extended (29-bit) identifiers, enabling interoperability across a wide range of CAN-based applications. It provides transmit and receive buffering, message filtering, error detection and handling, bus arbitration, and programmable bit-timing control to support robust network communication. CoreCAN is designed for FPGA- and ASIC-based designs and interfaces with host processors through a memory-mapped register set, simplifying system integration. The core supports classic CAN frames with payload sizes up to 8 bytes and includes features for monitoring bus status and managing communication errors. CoreCAN is suitable for automotive, industrial automation, and embedded control applications that require standards-compliant CAN 2.0 communication. The IP does not support CAN FD (Flexible Data Rate) functionality.
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Features and Benefits
- Flexible Message Filtering:
- Each of the 32 receive buffers includes configurable filters for ID, IDE, RTR, and data bytes.
- Multi-Buffer Reception:
- Allows multiple messages with the same ID to be stored in separate buffers.
- Automatic RTR Handling:
- Responds to Remote Transmission Requests with optional interrupt generation.
- Priority-Based Transmission:
- Transmit buffers support programmable priority for controlled message arbitration.
- Message Abort Support:
- Enables immediate cancellation of pending transmissions.
- Single-Shot Transmission Mode:
- Sends messages once without auto-retransmission on error or arbitration loss.
- Dedicated Memory Buffers:
- Separate 32-message memory blocks for transmit and receive paths.
- System Bus Interface:
- AMBA 3 Advanced Peripheral Bus (APB) Interface.
Documentation
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