Microchip Technology Inc
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SY87725L

Status: Samples Available

Features:

  • Single 3.3V supply and 1W typ. power consumption
  • 2.5G/1.25G/625Mbps downstream
  • 1.25G/625M/156Mbps upstream
  • 4-bit Serdes with LVDS interfaces
  • Serial Data input sensitivity of 30mV typical
  • Training mode for fast lock acquisition
  • Link Fault Indicator (LFIN: "HIGH" = Locked)
  • Separate training and MUX synthesizers
  • Loop back function for diagnostics
  • TTL-CML Translator for MAC-to-Laser diode driver burst control
  • Selectable double data rate option for low cost FPGA/ASIC MAC implementation
  • Available in Pb-Free (10mm x 10mm) 64-pin ePad-TQFP
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Device Overview

Summary

The SY87725L is a single chip transceiver for data rates up to 2.5Gbps. On the receive side, it includes a complete clock recovery and data retiming circuit with an integrated 4-bit serial-to-parallel data converter. On the transmit side, it includes a synthesizer with an integrated 4-bit parallel-to-serial data converter. The SY87725L receiver has a synthesizer that generates an internal clock from an externally supplied TTL or PECL REFCLK that can be either 155.52MHz or 77.76MHz. This internal clock can be used by the clock recovery PLL if an absence of transitions on the input serial data stream prevents normal clock recovery. This enables it to provide a stable clock source in the absence of transitions on the incoming serial data stream. The transmit synthesizer uses the CLKIN parallel data clock to generate its own serial rate clock locked to CLKIN. This enables the transmit and receive to operate at different data rates. The serial interface for both the transmit and receive functions feature industry standard high-speed differential CML I/O. The parallel interfaces feature high-speed LVDS I/O with an internal 100Ω termination on the LVDS inputs. The first bit for the serial-to-parallel conversion can be moved using the RCV_SYNC input. The RCV_SYNC input enables the parallel word boundary to move up in time by one bit time for each pulse. This allows it to in effect “swallow” one bit each time the RCV_SYNC pulse is asserted.

Additional Features
    • Single 3.3V supply and 1W typ. power consumption
    • 2.5G/1.25G/625Mbps downstream
    • 1.25G/625M/156Mbps upstream
    • 4-bit Serdes with LVDS interfaces
    • Serial Data input sensitivity of 30mV typical
    • Training mode for fast lock acquisition
    • Link Fault Indicator (LFIN: "HIGH" = Locked)
    • Separate training and MUX synthesizers
    • Loop back function for diagnostics
    • TTL-CML Translator for MAC-to-Laser diode driver burst control
    • Selectable double data rate option for low cost FPGA/ASIC MAC implementation
    • Available in Pb-Free (10mm x 10mm) 64-pin ePad-TQFP

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11/11/2015
758KB

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