Quantum computing is poised to break widely used cryptographic algorithms like RSA and ECC, which protect everything from online banking to government secrets. Post-Quantum Cryptography (PQC) is the next generation of cryptographic algorithms designed to resist quantum attacks. Even before quantum computers arrive, adversaries can harvest encrypted data and decrypt it later, making PQC a critical investment for future-proof security.
We are driving the post-quantum transition with a growing portfolio of PQC-ready hardware, secure provisioning services and crypto-agile architectures and empowering you to meet global standards and accelerate compliance with mandates such as CNSA 2.0, which begins in 2025 and phases in through 2033.
To counter quantum threats, the NSA introduced CNSA 2.0, a roadmap for adopting quantum-resistant cryptography. Unlike CNSA 1.0, which used vulnerable public key algorithms, CNSA 2.0 embraces secure methods like lattice-based encryption. Symmetric algorithms such as AES-256 and SHA-2 remain effective with increased key sizes.
Key considerations for transitioning:
We have integrated PQC at the hardware root of trust, enabling secure operations from power-on to end of life. Our approach, which mirrors industry leaders, is to embed quantum-resistant algorithms directly into our product architecture to provide crypto agility and compliance with standards like CNSA 2.0, FIPS 203, FIPS 204 and FIPS 205.
Hardware-based implementations of PQC offer several key advantages:
The low-power, highly configurable MEC175xB family of embedded controllers is designed for notebook and storage enclosure platforms. It features an Arm® Cortex®-M4F processor, advanced I/O capabilities, secure boot with customizable firmware and robust power management. With support for modern and legacy interfaces, hardware-based cryptography and flexible Flash-sharing mechanisms, it enables secure and efficient system control in ACPI-compliant architectures.
The Switchtec PFX Gen 6 fanout PCIe switch family comprises high-reliability PCIe switches supporting up to 160 lanes, 20 ports and 10 stacks; hot-plug and surprise-plug controllers for each port; advanced error containment and comprehensive diagnostics and debug capabilities; a variety of I/O interfaces; and an integrated MIPS® processor, with bifurcation at x8 and x16.
Access PQC documentation, developer tools and secure provisioning services through myMicrochip. Our team is ready to help you future-proof your designs and meet compliance requirements.