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ZL30102

PDH System Synchronizer

Status: In Production

Features:

  • Accepts three input references and synchronizes to any combination of 8 kHz, 1.544, 2.048, 8.192 or 16.384 MHz inputs
  • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant primary and a secondary clocks
  • Provides a range of clock outputs: 1.544, 2.048, 3.088, 6.312 and 16.384 MHz and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz
  • Provides 5 styles of 8 kHz framing pulses
  • Less than 0.6 nspp jitter on all output clocks
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30102 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 4/4E timing specifications. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter.
The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

Additional Features
  • Accepts three input references and synchronizes to any combination of 8 kHz, 1.544, 2.048, 8.192 or 16.384 MHz inputs
  • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between redundant primary and a secondary clocks
  • Provides a range of clock outputs: 1.544, 2.048, 3.088, 6.312 and 16.384 MHz and either 4.096 and 8.192 MHz or 32.768 and 65.536 MHz
  • Provides 5 styles of 8 kHz framing pulses
  • Less than 0.6 nspp jitter on all output clocks
  • Holdover frequency accuracy of 1x10-7
  • Attenuates wander from 1.8 Hz
  • Provides Lock, Holdover and selectable Out of Range indication
  • Simple hardware control interface
  • Manual and Automatic hitless reference switching
  • Supports Telcordia GR-1244-CORE Stratum 4 and 4E
  • Supports ITU-T G.823 and G.824 for 2048 kbs and 1544 kbs interfaces
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
1.8 Hz
Inputs
3
Diff Outputs
N/A
CMOS Outputs
10
Typical Jitter (12kHz-20MHz) fs RMS
PDH Interfaces
Diff InputFreq Range
8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
Output Freq Range
65.536 MHz
NV Memory
N/A
NCO ppb
N/A
Align
3

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Data Sheets

  
553KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30102QDG1
0.286700
2.562500
64
TQFP
10x10x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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