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MIV_RV32IMA_L1_AXI

The MIV_RV32IMA_L1_AXI is a softcore processor designed to implement the RISC-V instruction set for use in Microsemi FPGAs. The processor is based on the Rocket-Chip RISC-V core.


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Features and Benefits

  • Designed for low power ASIC microcontroller and FPGA soft-core implementations.
  • Integrated 8Kbytes instructions cache and 8Kbytes data cache.
  • A Platform-Level Interrupt Controller (PLIC) can support up to 31 programmable interrupts with a single priority level.
  • Supports the RISC-V standard RV-32IMA ISA.
  • On-Chip debug unit with a JTAG interface.
  • Optional AXI4 or pseudo AXI3 interfaces dedicated to peripheral IO and memory/data cache operations respectively

    • Licensing Options

    Free with any Libero License

    Documentation

    Title
    HB0823_MIV_RV32IMA_L1_AXI.pdf Download