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PL613-21

Status: In Production

Features:

  • Designed for PCB space savings with 3 low-power Programmable PLLs
  • Ultra Low-Power Consumption
  • Ultra-Low Power Down Mode, <5µA Typical
  • CLK1 Capable of Generating 32.768kHz
  • Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.8V to 3.3V ±10%
  • Individual PLL Power Down Control
  • ≤65MHz @ 1.8V operation
  • ≤90MHz @ 2.5V operation
  • ≤125MHz @ 3.3V operation
  • Fundamental Crystal: 10MHz to 40MHz
  • Reference Input: 10MHz to 200MHz
  • Active Low or Hi-Z Disabled Output State
  • 1.8V to 3.3V ±10% Core Power Supply
  • 1.8V to 3.3V ±10% Buffer Power Supply
  • 0°C to +70°C
  • -40°C to +85°C
  • Available in GREEN/RoHS compliant 3mm x 3mm QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The PL613-21 is an advanced three PLL design based on PicoPLL, the world’s smallest programmable clock technology. This advanced technology allows the PL613-21 to fit in to a small 3mm x 3mm QFN package for high performance, low-power, small form-factor applications. By using the individual output buffer VDD pins, the PL613-21 can support multiple output voltage requirements. In addition, CLK1 has the ability to generate kHz outputs and is ideal for generating 32.768kHz outputs.The unique power down features of the PL613-21 allows the user to shut down individual PLLs when the corresponding clock output is disabled using the PDB pins. The output drive strength can be individually programmed on each output to Low (4mA), Standard (8mA) or High (16mA) drive. In addition, the disabled state of the clock outputs can be programmed as Hi-Z or Active Low.Besides its small form factor and multiple outputs that can reduce overall system costs, the PL613-21 offers superior phase noise, jitter and power consumption performance.

Additional Features
    • Designed for PCB space savings with 3 low-power Programmable PLLs
    • Ultra Low-Power Consumption
    • Ultra-Low Power Down Mode, <5µA Typical
    • CLK1 Capable of Generating 32.768kHz
    • Individual Output Buffer VDD Pins for Flexible Output Voltages, 1.8V to 3.3V ±10%
    • Individual PLL Power Down Control
    • Output Frequency (based on VDD_CORE voltage):
      • ≤65MHz @ 1.8V operation
      • ≤90MHz @ 2.5V operation
      • ≤125MHz @ 3.3V operation
    • Input Frequency:
      • Fundamental Crystal: 10MHz to 40MHz
      • Reference Input: 10MHz to 200MHz
    • Active Low or Hi-Z Disabled Output State
    • 1.8V to 3.3V ±10% Core Power Supply
    • 1.8V to 3.3V ±10% Buffer Power Supply
    • Temperature range:
      • 0°C to +70°C
      • -40°C to +85°C
    • Available in GREEN/RoHS compliant 3mm x 3mm QFN package
Parametrics
Name
Value
Product Type
Low Power Clock Generators
PLLs
3
Input Frequency (MHz) Crystal
10-40
Input Frequency (MHz) Reference
10-200
# of Outputs
4
Voltage
1.8 - 3.3
PDB
True
OE
False
FSEL
False
CSEL
False
CLK
True
Output Logic
LVCMOS
Function
Programmable, PDB, Varying Voltage on Outputs
Ultra Low Power
True
Output Frequency Min. (MHz)
0.032
Output Frequency Max. (MHz)
125

Documents

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12/11/2015
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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
PL613-21-001
0.106667
16
WQFN
3x3x0.75mm
NiPdAu
e4
PL613-21-002
0.106667
16
WQFN
3x3x0.75mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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