MACSEC AES128 is a balanced core implementing the MACsec protocol as standardized in IEEE Std 802.1AE-2018. It uses Advanced Encryption Standard with 256 bits long key in Galois Counter Mode (AES-GCM) to protect data confidentiality, data integrity and data origin authentication. The cipher suite is denoted either as GCM-AES-XPN-256 if the eXtended Packet Numbering (XPN) is in use, or as GCM-AES-XPN-256 if XPN is not in use. This core is best suited for traffic on 1 Gbps links, and can be deployed using low-cost FPGA families.It can also be retrofitted to existing FPGA designs without requiring a board re-spin, either if there are enough FPGA resources available or if a pin-compatible FPGA with additional resources can be used.
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Features and Benefits
- Optimized resource requirements:
- Does not require any multipliers, DSPBlocks or internal memory in a typical Microchip® FPGA implementation.
- Performance:
- Achieves a high throughput up to 100s of Gbps compliant with NIST Standards.
- The key, initialization vector (IV), and the mode of operation can be dynamically updated for every 128-bit data clock.
- Standard Compliance:
- Fully compliant with MACsec protocol as standardized in IEEE Std 802.1AE-2018.
- The cipher suite (GCM-AES-256 or GCM-AES-XPN-256) is fully compliant with the Advanced Encryption Algorithm (AES) standard, as well as with the Galois Counter Mode (GCM) standard.
- Passes the relevant test vectors specified in Annex C of IEEE Std 802.1AE-2018
- Easy Integration :
- Pure RTL without hidden CPU or software components.
- Vendor agnostics FPGA/ASIC implementation.
Licensing Options
For additional information contact: sales@xiphera.com or visit Xiphera
Documentation
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