Status: In Production
The KSZ8567 is a fully integrated layer 2, managed, seven-port 10/100 Ethernet switch with numerous advanced features, designed to exceed Automotive AEC-Q100 Grade 2 (-40°C to +105°C) and EMC requirements . Five of the seven ports incorporate 10/100 Mbps PHYs. The other two ports have 1000 Mbps MAC interfaces that can be configured as SGMII, RGMII, MII or RMII. Either of these may connect directly to a host processor or to an external PHY.
Full register access is available by SPI or I2C interfaces, and by optional in-band management via any of the data ports. PHY register access is provided by a MIIM interface.
Security features include support for IEEE 802.1X port-based authentication and Access Control List (ACL) filtering.
As a member of the EtherSynch® product family, the KSZ8567 incorporates full hardware support for the IEEE 1588v2 Precision Time Protocol (PTP), including hardware time-stamping at all PHY-MAC interfaces, and a high-resolution hardware “PTP clock”. IEEE 1588 provides sub-microsecond synchronization for a range of industrial Ethernet applications.
The KSZ8567 fully supports the IEEE family of audio video bridging (AVB) standards, which provide for high quality of service (QoS) for latency sensitive traffic streams over Ethernet. Time-stamping and time-keeping features support IEEE 802.1AS time synchronization. All ports feature credit based traffic shapers for IEEE 802.1Qav, and a time aware scheduler as proposed for IEEE 802.1Qbv.
An assortment of power-management features including
Energy-Efficient Ethernet (EEE) have been designed in to
satisfy energy efficient environments.
Microchip's complimentary and confidential LANCheck® online design review service is available for customers who have selected our products for their application design-in. The LANCheck online design review service is subject to Microchip's Program Terms and Conditions and requires a myMicrochip account.
Non-blocking wire-speed Ethernet switching fabric
IEEE802.1AS (AVB) time synchronization support
IEEE802.1Qav (AVB) credit based traffic shaper
Time aware traffic scheduler with low latency cut- through mode
IEEE1588v2 Precision Time Protocol support
Time-stamping on all ports
Precision GPIO pin timed to the AVB/1588 clock
Full-featured forwarding and filtering control, including Access Control List (ACL) filtering
IEEE802.1X support (Port-Based Network Access Control)
IEEE802.1Q VLAN supportfor 128 active VLAN groups and the full range of 4096 VLAN IDs
IEEE802.1p/Q tag insertion or removal on a per port basis and support for double-tagging
VLAN ID tag/untag options on per port basis
IEEE802.3x full-duplex flow control and half-duplex back pressure collision control
IGMPv1/v2/v3 snooping for multicast packet filtering
IPv6 multicast listener discovery (MLD) snooping
QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per-port basis on four priority levels
IPv4/IPv6 QoS support
Programmable rate limiting at ingress and egress ports
Broadcast storm protection
Four priority queues with dynamic packet mapping for IEEE802.1p, IPv4 DIFFSERV, IPv6 TrafficClass
MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
Self-address filtering for implementing ring topologies
I2C Interface to access all registers
MII management (MIIM, MDC/MDIO 2 wire) interface to access all PHY registers per IEEE 802.3 specification
In-band management to access all registers via any of the seven ports, strap enabled
I/O pin strapping facility to set certain register bits from I/O pins at reset time
This is the evaluation board for the KSZ9477S 7-Port Gigabit Ethernet Switch (also KSZ9567 and KSZ8567). The SAMA5D3 processor manages the switch and includes the ATECC508A security encoder. The DSC1101 is the reference clock for GigE communication. The EVB can be used to implement IEEE 1588v2, AVB and DLR/HSR (available on KSZ9477 only) network redundancy. Combine multiple boards to implement...
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