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ZL30152

1-Ch Line Card Synchronizer

Status: In Production

Features:

  • Programmable synthesizers generate any clockrate from 1 kHz to 750 MHz
  • Precision synthesizers generate clocks with jitter below 0.7 ps RMS for 10 G PHYs
  • Programmable digital PLL synchronize to any clockrate from 1 kHz to 750 MHz
  • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
  • Digital PLL filter jitter from 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
  • Automatic hitless reference switching and digital holdover on reference fail
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30152 Universal Clock Translator, part of Microsemi's ClockCenter platform of Synchronous Clock devices, delivers industry leading synchronization performance for high-speed complex applications. The highly integrated and programmable solution provides translation from any input reference frequency to any output clock frequency with jitter performance that can directly drive 10 G PHY devices.
The ZL30152 accepts 2 single ended or differential input references and generates 6 high performance programmable clock outputs. The highly integrated solution allows designers to replace multiple components with a single chip, simplifying design and reducing component count and power.

Additional Features
  • Programmable synthesizers generate any clockrate from 1 kHz to 750 MHz
  • Precision synthesizers generate clocks with jitter below 0.7 ps RMS for 10 G PHYs
  • Programmable digital PLL synchronize to any clockrate from 1 kHz to 750 MHz
  • Flexible two-stage architecture translates between arbitrary data rates, line coding rates and FEC rates
  • Digital PLL filter jitter from 14 Hz, 28 Hz, 56 Hz, 112 Hz, 224 Hz, 448 Hz or 896 Hz
  • Automatic hitless reference switching and digital holdover on reference fail
  • Two reference inputs configurable as single ended or differential
  • Four LVPECL outputs and two LVCMOS outputs
  • Operates from a single crystal resonator or clock oscillator
  • Customer defined default device configuration, including input/output frequencies, is available via OTP(One Time Programmable) memory
  • Dynamically configurable via SPI/I2C
  • Applications/Uses
  • - Clock Generation for Physical Line Interface:
    • - SONET/SDH, OC-192/OC-48
    • - SONET/SDH with FEC
    • - 10G Base X, R and W
    • - 100 BaseX, GE, Fibre channel
  • - Clock Generation and Distribution for back plane Interface:
    • - TDM, Telecom Bus, Utopia, SBI
    • - Rapid-IO, PCI-Express, serial MII, Star Fabric, XAUI
Parametrics
Name
Value
Type
Advanced
DPLLs or Paths
1
DPLL Bandwidth (Hz)
14-896
Inputs
2 D/SE
Diff Outputs
4
CMOS Outputs
2
Low-Jitter Synthesizers
1
Typical Jitter (12kHz-20MHz) fs RMS
700
Diff InputFreq Range
1 kHz-750 MHz
Output Freq Range
1 kHz-750 MHz
NV Memory
OTP
NCO ppb
-
Align
-

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Data Sheets

  
1020KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30152GGG2
0.313500
1.361539
64
LBGA
9x9x1.72mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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