Microchip logo
  • All
  • Products
  • Documents
  • Applications Notes
product primary image

ZL30110

PDH/SDH System Synchronizer

Status: In Production

Features:

  • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
  • Provides DPLL lock and reference fail indication
  • Automatic free run mode on reference fail
  • DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
  • Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
  • Minimal input to output and output to output skew
View More
Overview
Documents
Development Environment
RoHS Information
Add to Cart

Device Overview

Summary

The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.

Additional Features
  • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
  • Provides DPLL lock and reference fail indication
  • Automatic free run mode on reference fail
  • DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
  • Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
  • Minimal input to output and output to output skew
  • 25 MHz external master clock source: clock oscillator or crystal
  • Simple hardware control interface
  • Provides a range of output clocks:
    • 65.536 MHz TDM clock locked to the input reference
    • General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
    • General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
922
Inputs
1
CMOS Outputs
9
Typical Jitter (12kHz-20MHz) fs RMS
<5000
Diff InputFreq Range
8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
Output Freq Range
65.536 MHz
NV Memory
N/A
NCO ppb
N/A

Documents

Jump to:

Data Sheets

  
320KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30110LDF1
0.070100
0.330000
32
VQFN
5x5x1mm
Matte Tin
e3
ZL30110LDG1
0.070100
0.571429
32
VQFN
5x5x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

Buy from Microchip

Grid
View
Table
View
Filter:
Apply
Clear
Only show products with samples
Product
Leads
Package Type
Temp Range
Packing Media
5K Pricing
Buy