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ZL30107

PDH/SDH System Synchronizer

Status: In Production

Features:

  • Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock
  • Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock
  • Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover
  • In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a low cost crystal (XTAL)
  • In Synchronous mode, the DPLL automatically synchronizes to one of a pre-defined set of frequencies including 2 kHz, 8 kHz, 64 kHz, 1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz.
  • Configurable to accept a 25 MHz input reference
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30107 provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures. Integrating independent analog and digital PLLs, the device synchronizes with standard telecom and Ethernet clocks and generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock. Backed by Microchip's leading timing and synchronization expertise, no competing device can match the performance and level of integration at the price point supported by the ZL30107 device.

Additional Features
  • Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock
  • Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock
  • Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover
  • In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a low cost crystal (XTAL)
  • In Synchronous mode, the DPLL automatically synchronizes to one of a pre-defined set of frequencies including 2 kHz, 8 kHz, 64 kHz, 1.544 MHz, 2.048 MHz, 6.48 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz, 38.88 MHz, 77.76 MHz.
  • Configurable to accept a 25 MHz input reference
  • Automatic entry into Asynchronous Holdover mode when all input references fail
  • Lock indicator pin
  • Input reference status monitors
  • Programmable loop bandwidth of 14 Hz, 28 Hz, or 890 Hz
Parametrics
Name
Value
Type
PDH/SDH
DPLL Bandwidth (Hz)
14 Hz, 28 Hz, or 890 Hz
Inputs
3
CMOS Outputs
1
Output Freq Range
25 MHz
NV Memory
N/A
NCO ppb
N/A

Documents

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Data Sheets

  
182KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30107GGG2
0.313500
1.361539
64
LBGA
9x9x1.72mm
SAC305
e1
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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