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ZL30106

PDH/SDH System Synchronizer

Status: In Production

Features:

  • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
  • Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
  • Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides automatic entry into Holdover and return from Holdover
  • Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication
  • Selectable loop filter bandwidth of 29 Hz or 922 Hz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.
The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.
The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

Additional Features
  • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs
  • Supports output wander and jitter generation specifications for SONET/SDH and PDH interfaces
  • Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides automatic entry into Holdover and return from Holdover
  • Manual and automatic hitless reference switching Provides lock, holdover and accurate reference fail indication
  • Selectable loop filter bandwidth of 29 Hz or 922 Hz
  • Provides a range of clock outputs:
    • 2.048 MHz (E1), 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
    • 19.44 MHz (SONET/SDH)* 1.544 MHz (DS1) and 3.088 MHz
    • a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3)Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
29 Hz or 922 Hz
Inputs
3
Diff Outputs
N/A
CMOS Outputs
11
Typical Jitter (12kHz-20MHz) fs RMS
10G/OC-192/STM-64
Diff InputFreq Range
2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
Output Freq Range
65.536 MHz
NV Memory
N/A
NCO ppb
N/A
Align
4

Documents

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Data Sheets

  
596KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30106QDG1
0.286700
2.562500
64
TQFP
10x10x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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