Status: Not Recommended for new designs
The SY10/100E131 are high-speed quad master slave D-type flip-flops with differential outputs designed for use in new, high-performance ECL systems. The flip-flops may be individually clocked by holding CC (Common Clock) at a logic LOW and then using the four individual CE (Clock Enable CE0-CE3) inputs to accomplish such clocking. Alternatively, all four flip-flops can be clocked in common by holding the CE inputs LOW and then using CC to clock the data. In the common clock mode, the CE input acts as a control that passes the CC signal to the flip-flop. Data is clocked into the flip-flop on the rising edge of the output of the logical OR operation between CE and CC (data enters the master when both CC and CE are LOW and data transfers to the slave when either CE or CC, or both, go HIGH).Asynchronous set and reset controls are provided. The reset controls are individual and the set controls are pairwise.
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