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SST49LF160C

Status: End of Life

Features:

  • Organized as 2M x8
  • Conforms to LPC Interface Specification– Support Single-Byte LPC Memory Read/WriteCycles
  • Single 3.0-3.6V Read and Write Operations
  • LPC Mode– 5-signal LPC bus interface for both in-systemand factory programming using programmerequipment– 33 MHz clock frequency operation– WP#/AAI and TBL# pins provide hardware Writeprotect for entire chip and/or top Boot Block– Block Locking Registers for individual block Read-Lock, Write-Lock, and Lock-Down protection– 5 GPI pins for system design flexibility– 4 ID pins for multi-chip selection– Status register for End-of-Write detection– Program-/Erase-SuspendRead or Write to other blocks duringProgram-/Erase-Suspend
  • Two-cycle Command Set
  • Security ID Feature– 256-bit Secure ID space- 64-bit Unique Factory Pre-programmedDevice Identifier- 192-bit User-Programmable OTP
  • Superior Reliability– Endurance: 100,000 Cycles (typical)– Greater than 100 years Data Retention
  • Low Power Consumption– Active Read Current: 12 mA (typical)– Standby Current: 10 µA (typical)
  • Uniform 4 KByte sectors– 35 Overlay Blocks: one 16-KByte Boot Block,two 8-KByte Parameter Blocks, one 32-KbyteParameter Block, thirty-one 64-KByte MainBlocks.
  • Fast Sector-Erase/Program Operation– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Program Time: 7 µs (typical)
  • Auto Address Increment (AAI) for Rapid FactoryProgramming (High Voltage Enabled)– RY/BY# pin for End-of-Write detection– Multi-Byte Program– Chip Rewrite Time: 4 seconds (typical)
  • Packages Available– 32-lead PLCC
  • All non-Pb (lead-free) devices are RoHS compliant
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Device Overview

Summary

The SST49LF160C flash memory device is designed to interface with host controllers (chipsets) that support a lowpin-count (LPC) interface for system firmware applications. The SST49LF160C device complies with the LPC Interface Specification. The LPC interface operates with 5 signal pins versus 32 pins of a 8-bit parallel flash memory. This frees up pins on the ASIC host controller resulting in lower ASIC costs and a reduction in overall system costs due to simplified signal routing.

EOL Notification

Additional Features
    • Organized as 2M x8
    • Conforms to LPC Interface Specification– Support Single-Byte LPC Memory Read/WriteCycles
    • Single 3.0-3.6V Read and Write Operations
    • LPC Mode– 5-signal LPC bus interface for both in-systemand factory programming using programmerequipment– 33 MHz clock frequency operation– WP#/AAI and TBL# pins provide hardware Writeprotect for entire chip and/or top Boot Block– Block Locking Registers for individual block Read-Lock, Write-Lock, and Lock-Down protection– 5 GPI pins for system design flexibility– 4 ID pins for multi-chip selection– Status register for End-of-Write detection– Program-/Erase-SuspendRead or Write to other blocks duringProgram-/Erase-Suspend
    • Two-cycle Command Set
    • Security ID Feature– 256-bit Secure ID space- 64-bit Unique Factory Pre-programmedDevice Identifier- 192-bit User-Programmable OTP
    • Superior Reliability– Endurance: 100,000 Cycles (typical)– Greater than 100 years Data Retention
    • Low Power Consumption– Active Read Current: 12 mA (typical)– Standby Current: 10 µA (typical)
    • Uniform 4 KByte sectors– 35 Overlay Blocks: one 16-KByte Boot Block,two 8-KByte Parameter Blocks, one 32-KbyteParameter Block, thirty-one 64-KByte MainBlocks.
    • Fast Sector-Erase/Program Operation– Sector-Erase Time: 18 ms (typical)– Block-Erase Time: 18 ms (typical)– Program Time: 7 µs (typical)
    • Auto Address Increment (AAI) for Rapid FactoryProgramming (High Voltage Enabled)– RY/BY# pin for End-of-Write detection– Multi-Byte Program– Chip Rewrite Time: 4 seconds (typical)
    • Packages Available– 32-lead PLCC
    • All non-Pb (lead-free) devices are RoHS compliant
Parametrics
Name
Value
Density
16 Mbit
Op. Volt Range (V)
3 to 3.6
Max. Clock Freq.
33 MHz
Temp Range (°C)
0°C to +70°C
Endurance
100,000

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