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SST49LF008A

3.0V to 3.6V 8Mbit Firmware Flash

Status: In Production

Features:

  • Firmware Hub for Intel 8xx Chipsets
  • 8 Mbit SuperFlash memory array for code/datastorage– 1024K x8
  • Flexible Erase Capability– Uniform 4 KByte Sectors– Uniform 64 KByte overlay blocks– 64 KByte Top Boot Block protection– Chip-Erase for PP Mode Only
  • Single 3.0-3.6V Read and Write Operations
  • Superior Reliability– Endurance:100,000 Cycles (typical)– Greater than 100 years Data Retention
  • Low Power Consumption– Active Read Current: 6 mA (typical)– Standby Current: 10 µA (typical)
  • Sector-Erase Time: 18 ms (typical)
  •  Block-Erase Time: 18 ms (typical)
  • Chip-Erase Time: 70 ms (typical)
  • Byte-Program Time: 14 µs (typical)
  • Chip Rewrite Time: 15 seconds (typical)
  • Single-pulse Program or Erase– Internal timing generation
  • Two Operational Modes– Firmware Hub Interface (FWH) Mode forIn-System operation– Parallel Programming (PP) Mode for fastproduction programming
  • Firmware Hub Hardware Interface Mode– 5-signal communication interface supportingbyte Read and Write– 33 MHz clock frequency operation– WP# and TBL# pins provide hardware writeprotect for entire chip and/or top Boot Block– Block Locking Register for all blocks– Standard SDP Command Set– Data# Polling and Toggle Bit for End-of-Writedetection– 5 GPI pins for system design flexibility– 4 ID pins for multi-chip selection
  • Parallel Programming (PP) Mode– 11-pin multiplexed address and8-pin data I/O interface– Supports fast In-System or PROM programmingfor manufacturing
  • CMOS and PCI I/O Compatibility
  • Packages Available– 32-lead PLCC– 32-lead TSOP (8mm x 14mm)– 40-lead TSOP (10mm x 20mm)– Non-Pb (lead-free) packages available
  • All non-Pb (lead-free) devices are RoHS compliant
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Overview
Documents
Development Environment
Similar Devices
RoHS Information
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Device Overview

Summary

The SST49LF008A flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of PC-BIOS applications.

Additional Features
    • Firmware Hub for Intel 8xx Chipsets
    • 8 Mbit SuperFlash memory array for code/datastorage– 1024K x8
    • Flexible Erase Capability– Uniform 4 KByte Sectors– Uniform 64 KByte overlay blocks– 64 KByte Top Boot Block protection– Chip-Erase for PP Mode Only
    • Single 3.0-3.6V Read and Write Operations
    • Superior Reliability– Endurance:100,000 Cycles (typical)– Greater than 100 years Data Retention
    • Low Power Consumption– Active Read Current: 6 mA (typical)– Standby Current: 10 µA (typical)
    • Fast Sector-Erase/Byte-Program Operation
      • Sector-Erase Time: 18 ms (typical)
      •  Block-Erase Time: 18 ms (typical)
      • Chip-Erase Time: 70 ms (typical)
      • Byte-Program Time: 14 µs (typical)
      • Chip Rewrite Time: 15 seconds (typical)
      • Single-pulse Program or Erase– Internal timing generation
    • Two Operational Modes– Firmware Hub Interface (FWH) Mode forIn-System operation– Parallel Programming (PP) Mode for fastproduction programming
    • Firmware Hub Hardware Interface Mode– 5-signal communication interface supportingbyte Read and Write– 33 MHz clock frequency operation– WP# and TBL# pins provide hardware writeprotect for entire chip and/or top Boot Block– Block Locking Register for all blocks– Standard SDP Command Set– Data# Polling and Toggle Bit for End-of-Writedetection– 5 GPI pins for system design flexibility– 4 ID pins for multi-chip selection
    • Parallel Programming (PP) Mode– 11-pin multiplexed address and8-pin data I/O interface– Supports fast In-System or PROM programmingfor manufacturing
    • CMOS and PCI I/O Compatibility
    • Packages Available– 32-lead PLCC– 32-lead TSOP (8mm x 14mm)– 40-lead TSOP (10mm x 20mm)– Non-Pb (lead-free) packages available
    • All non-Pb (lead-free) devices are RoHS compliant
Parametrics
Name
Value
Density
8 Mbit
Op. Volt Range (V)
3 to 3.6
Max. Clock Freq.
33 MHz
Temp Range (°C)
0°C to +70°C
Endurance
100,000
Data Retention (Years)
100

Documents

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Application Notes

Brochures

12/19/2017
3698KB

Board Design Files

06/24/2015
4KB

MISC

06/23/2015
52KB

Development tools data is currently unavailable.

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SST49LF008A-33-4C-NHE
1.129000
2.333333
32
PLCC
11.5x14x3.37mm
Matte Tin
e3
SST49LF008A-33-4C-NHE-T
1.129000
1.896000
32
PLCC
11.5x14x3.37mm
Matte Tin
e3
SST49LF008A-33-4C-EIE
0.460600
2.833333
40
TSOP
10x20mm
Matte Tin
e3
SST49LF008A-33-4C-EIE-T
0.460600
0.200000
40
TSOP
10x20mm
Matte Tin
e3
SST49LF008A-33-4C-WHE
0.249700
1.442308
32
TSOP
8x14mm
Matte Tin
e3
SST49LF008A-33-4C-WHE-T
0.249700
0.333333
32
TSOP
8x14mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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