The SAMA5D27C-D1G System in Package (SiP) integrates the ARM® Cortex®-A5 processor-based SAMA5D27C MPU with 1 Gbit (128 Mbytes) of DDR2-SDRAM in a single package.  By combining the high-performance, ultra-low-power SAMA5D2 with DDR2-SDRAM in a single package, PCB routing complexity, area and number of layers is reduced in the majority of cases.  This makes board design easier and more robust by facilitating design for EMI, ESD and signal integrity.  This SiP targets applications using Linux OS and is available in a BGA289 package.

• ARM Cortex-A5 core:
  • Up to 500 MHz, ARMv7-A architecture, ARM TrustZone, NEON™ Media Processing Engine, 8 Kbyte Embedded Trace Buffer (ETB)
• Memory Architecture
  • Memory Management Unit
  • 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
  • 128-Kbyte L2 cache configurable to be used as an internal SRAM
  • 1Gb DDR2-SDRAM
  • One 128-Kbyte scrambled internal SRAM
  • One 160-Kbyte internal ROM, 64-Kbyte scrambled and maskable ROM embedding boot loader/Secure boot loader, 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
  • High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting the internal DDR2-SDRAM, including the “on-the-fly” encryption/decryption path
  • 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
• Low-Power Modes
  • Ultra Low-power mode with fast wakeup capability
  • Low-power Backup mode with 5-Kbyte SRAM and Sleep Walking™ features, Wakeup from up to nine wakeup pins, UART reception, analog comparison, Fast wakeup capability, Extended Backup mode with DDR2-SDRAM in Self-Refresh mode
• Peripherals
  • LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB
  • ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel 12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
  • Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier
  • One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
  • One Pulse Density Modulation Interface Controller (PDMIC)
  • One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host ports (UHPHS)
  • One 10/100 Ethernet MAC (GMAC)
    • Energy efficiency support (IEEE 802.3az standard), Ethernet AVB support with IEEE802.1AS time stamping, IEEE802.1Qav credit-based traffic-shaping hardware support, IEEE1588 Precision Time Protocol (PTP)
  • Two high-speed memory card hosts:
    • SDMMC0: SD 3.0, eMMC 4.51, 8 bits
    • SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
  • Many other serial, timer and A/D modules
  • Up to 128 I/Os
• Safety and Security:
  • Integrity Check Monitor based on SHA256, Crypto engine (SHA512, AES256, TDES), TRNG, tamper pins, Secure Boot Loader, Programmable fuse box, On-the-fly AES   encryption/decryption on DDR2-SDRAM and QSPI, 5 Kbytes of internal scrambled SRAM, 256 bits of scrambled and erasable registers, Independent watchdog, Main crystal clock failure detector