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ZL30265

6-Output Clock Generator int. EEPROM

Status: In Production

Features:

  • The two APLLs have fractional dividers and integer dividers to make four independent frequency families
  • Four Flexible Input Clocks: One crystal/CMOS input, Two differential/CMOS inputs, One single-ended/CMOS input
  • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS)
  • 6 Any-Frequency, Any-Format Outputs
  • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz)
  • Automatic self-configuration at power-up from internal EEPROM (see ZL30264 for internal EEPROM); up to 8 configurations pin-selectable
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Overview
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Development Environment
RoHS Information
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Device Overview

Summary

CREATE AND SAMPLE YOUR CUSTOM ZL30265 HERE

The miClockSynth ZL30265 high-performance, any-rate multiplier and clock generator simplifies board design by generating ultra-low-jitter clock signals from a single crystal or crystal oscillator while generating additional independent frequency families.

With up to four independent frequency families on one chip, best-in-class jitter performance, and two fractional-N APLLs with both a fractional and integer divider, the ZL30265 creates a complete clock-tree, improving design reliability, reducing bill of materials (BOM) cost, and simplifying design by replacing multiple crystals and peripheral timing components.

Additional Features
  • The two APLLs have fractional dividers and integer dividers to make four independent frequency families
  • Four Flexible Input Clocks: One crystal/CMOS input, Two differential/CMOS inputs, One single-ended/CMOS input
  • Any input frequency from 9.72MHz to 1.25GHz (300MHz max for CMOS)
  • Activity monitors, automatic or manual switching
  • Glitch-less clock switching by pin or register
  • 6 Any-Frequency, Any-Format Outputs
  • Any output frequency from 1Hz to 1045MHz
  • High-resolution frac-N APLL with 0ppm error
  • Output jitter from integer multiply and dividers as low as 0.17ps RMS (12kHz-20MHz)
  • Output jitter from fractional dividers is typically < 1ps RMS, many frequencies <0.5ps RMS
  • Each output has an independent divider and is configurable as LVDS, LVPECL, HCSL, 2xCMOS or HSTL
  • In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
  • Multiple output supply voltage banks with CMOS output voltages from 1.5V to 3.3V
  • Precise output alignment circuitry and per-output phase adjustment
  • Per-output enable/disable and glitch-less start/stop (stop high or low)
  • Automatic self-configuration at power-up from internal EEPROM (see ZL30264 for internal EEPROM); up to 8 configurations pin-selectable
  • External feedback for zero-delay applications
  • Numerically controlled oscillator mode
  • Spread-spectrum modulation mode
  • Generates PCIe 1, 2, 3, 4, 5 compliant clocks
  • Easy-to-configure design requires no external VCXO or loop filter components
  • SPI or I2C processor Interface
  • Core supply voltage options: 2.5V only, 3.3V only, 1.8V+2.5V or 1.8V+3.3V
  • Space-saving 8x8mm QFN56 (0.5mm pitch)
Parametrics
Name
Value
Product Type
Low-Jitter Clock Generators
# of Outputs
6
Voltage
2.5, 3.3
Output Logic
LVDS, LVPECL, HCSL, CMOS, HSTL
Output Frequency Min. (MHz)
0.000001
Output Frequency Max. (MHz)
1045

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30265LDG1Q05B
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05H
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265-LDG1-UB
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDF1
0.190800
0.548148
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q033
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q03V
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q040
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q048
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q04V
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05N
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05T
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDF1Q05T
0.190800
0.548148
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05V
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05W
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05X
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05Y
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q05Z
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q060
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q061
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q062
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q063
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q066
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q06B
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDF1Q05N
0.190800
0.548148
56
VQFN
8x8x1mm
Matte Tin
e3
ZL30265LDG1Q01G
0.190800
1.353846
56
VQFN
8x8x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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