Advancing FPGA Design With Libero® SoC Design Suite v2025.1: New Devices, Improved Performance and Broader Capabilities

Our latest release, Libero SoC Design Suite v2025.1, enables high-performance, power-efficient and security-focused Field-Programmable Gate Array (FPGA) designs. From expanded device support to toolchain upgrades, this update empowers engineers to accelerate development and confidently deploy Microchip FPGAs and System-on-Chip (SoC) FPGAs across a wide range of applications—from industrial to aerospace.

Below are some of the major enhancements and provide a breakdown of the new device support introduced with this release.

Major Toolchain Enhancements

Libero v2025.1 introduces support for the new PolarFire^® Core FPGAs and SoC FPGAs, as well as important updates:

Software Features and Enhancements

• Up to 1% Quality of Result (QoR) improvement for SmartFusion2, IGLOO2, PolarFire and PolarFire SoC and up to 2.4% QoR improvement for RT PolarFire using synthesized TMR flow
• Upgraded Synplify Pro ME tool to V-2023.09M-5 with RTG4 Dual-port Write-byte Enable, improved DSP inference report and Complete TMR report
• Upgraded the Identify tool to V-2023.09M-5 with RTG4 Pre-arm trigger and support for RT PolarFire and RT PolarFire SoC devices
• Upgraded ModelSim ME Pro and QuestaSim ME simulator tools to v2024.3
• SmartTime Enhancements: Better clock uncertainty handling, refined exception constraint resolution and more accurate bidirectional I/O delay analysis generated clock duty-cycle update
• Added support to program Micron MT25QL01G SPI-Flash devices
• SmartDebug Upgrades: DDR margin training, XCVR eye monitor improvements and persistent signal integrity settings

Enhanced IP Core Functionality

• DDR3/DDR4/LPDDR3 Controllers: Now support ZQCS commands, fast training simulation and reinitialization
• & SERDES: Improved presets for “Lock to Data with 2X Gain” mode, optimizing performance in noisy environments
• IOD Timing: RX_CLK_ODT_EN enhancements ensure safer LVDS failsafe operation; automatic repair support for source-synchronous TX hold violations

SmartHLS v2025.1 – Smarter, More Capable

• On-Board Execution: Soft-MiV RV32 now runs on SoC Flow
• Debugging: FIFO enhancements with full/empty labeling and metadata output
• Toolchain Upgrades: LLVM bumped to v15, GCC to v8.5, with C 14 as the new standard
• Performance: Enhanced QoR for split multiplication operations

PolarFire SoC Standalone MSS Configurator

• Version 2025.1 brings improved ECC lane mapping for x16 DDR3/DDR3L/DDR4 configurations, ensuring successful initialization and training

New Device Support

The v2025.1 release introduces full production support for a wide portfolio of PolarFire and PolarFire SoC devices, including extended, industrial and automotive temperature grades.

NEW! PolarFire FPGA – Core Devices

NEW! PolarFire SoC – Core Devices

PolarFire FPGA – Automotive TGrade2

PolarFire SoC – Automotive TGrade2

PolarFire SoC – Military Grade

RT PolarFire

• RTPF500ZT/ZTS/ZTL/ZTLS: New FC1509 package
• SSN analysis for CG1509 package for RTPF500ZT/TS/TL/TLS and RTPF500T/TS/TL/TLS devices

RT PolarFire SoC

• RTPFS460ZT/ZTS/ZTL/ZTLS: New FC1509 package
• Programming and SmartDebug support for RTPFS460ZT/ZTS/ZTL/ZTLS and RTPFS160ZT/TS/TL/TLS devices
• PFSOC_SCSM: Enable SC_WAKE control by dynamic signals from fabric logic to allow temporary exit from System Controller Suspend mode to perform System Services
  

The Libero SoC Design Suite v2025.1 release solidifies our leadership in secure, low-power and highly configurable FPGAs. With expanded device coverage, enhanced simulation fidelity and optimized tool performance, this release is built for developers seeking scalable, future-proof solutions in demanding edge, industrial and aerospace environments. To learn more or download the latest Libero SoC Design Suite v2025.1 release, visit the Microchip Hardware Design Tools page.