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dsPIC33CH512MP206

100 MHz Dual-Core 16-bit DSC

Status: In Production

Features:

  • Master Core 90 MIPS and Slave Core 100 MIPS Operation
  • Independent Peripherals for Master Core and Slave Core
  • 4 x 12-bit 3.5 MSPS ADCs: 34 Channels
  • High Speed PWMs with 250ps resolution, 12x2 Channels
  • Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
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Overview
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Development Environment
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Device Overview

Summary

Microchip’s dsPIC33CH family of digital signal controllers (DSCs) feature dual 90 & 100 MIPS 16-bit dsPIC® DSC cores with integrated DSP and enhanced on-chip peripherals. These DSCs enable the design of high-performance, precision motor control systems that are more energy efficient, quieter in operation and provide extended motor life. They can be used to control BLDC, PMSM, ACIM, SR and stepper motors. These DSCs enable the design of switched mode power supplies such as AC/DC, DC/DC, UPS and PFC, providing high-precision digital control of Buck, Boost, Fly-Back, Half-Bridge, Full-Bridge, LLC and other power circuits to reach the highest possible energy efficiency.  These devices are also ideal for many high-performance general-purpose and robust applications.

Additional Features
  • Operating Conditions:
    • 3V to 3.6V, -40°C to +150°C
  • Core: Dual 16-Bit dsPIC33CH CPUs
    • Master Core 90 MIPS and Slave Core 100 MIPS Operation
    • Independent Peripherals for Master Core and Slave Core
    • Configurable Shared Resources for Master Core and Slave Core
    • Fast 6-Cycle Divide
    • Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
    • Code Efficient (C and Assembly) Architecture
    • 40-Bit Wide Accumulators
    • Single-Cycle (MAC/MPY) with Dual Data Fetch
    • Single-Cycle, Mixed-Sign MUL Plus 6-Cycle Hardware Divide
    • 32-Bit Multiply Support
    • Five Sets of Interrupt Context Selected Registers and Accumulators per Core for Fast Interrupt Response
    • Zero Overhead Looping
    • High Performance Peripherals for Real Time Control:
    • 4 x 12-bit 3.5 MSPS ADCs: 34 Channels
    • High Speed PWMs with 250ps resolution, 12x2 Channels
    • Optimized for high-performance digital power, motor control and applications requiring sophisticated algorithms
  • Master Core features:
    • Core Frequency 90 MIPS @ 180 MHz
    • Program Flash: 512/256 Kbytes Dual Partition with LiveUpdate
    • Data RAM: 48/32 Kbytes
    • 16-Bit Timer: 1
    • DMA: 6
    • SCCP (Capture/Compare/Timer): 8
    • UART: 2
    • SPI/I2S: 2
    • I2C: 2
    • CAN Flexible Data-Rate (FD): 2 ('50x devices only)
    • SENT: 2
    • CRC: 1
    • QEI: 1
    • PTG:1
    • CLC: 4
    • 16-Bit High-Speed (250ps) PWM: 4x2
    • 12-bit, 3.5 Msps ADC: 1, 16 Channels
    • Digital Comparator: 4
    • 12-Bit DAC/Analog CMP Module: 1
    • Watchdog Timer: 1
    • Deadman Timer: 1
    • Breakpoints: 3 complex, 5 simple
    • Oscillator: 1
  • Slave Core features:
    • Core Frequency 100 MIPS @ 200 MHz
    • Program Memory: 72 Kbytes (PRAM) Dual Partition with LiveUpdate
    • Data RAM: 16 Kbytes
    • 16-Bit Timer: 1
    • DMA: 2
    • SCCP (Capture/Compare/Timer): 4
    • UART: 1
    • SPI/I2S: 1
    • I2C: 1
    • QEI: 1
    • CLC: 4
    • 16-Bit High-Speed (250ps) PWM: 8x2 Channels
    • 12-bit, 3.5 Msps ADC: 3, 18 Channels
    • Digital Comparator: 4
    • 12-Bit DAC/Analog CMP Module: 3
    • Watchdog Timer: 1
    • Deadman Timer: 1
    • Breakpoints: 1 complex, 2 simple
    • Oscillator: 1
  • Clock Management:
    • Internal Oscillator
    • Programmable PLLs and Oscillator Clock Sources
    • Master Reference Clock Output
    • Slave Reference Clock Output
    • Fail-Safe Clock Monitor (FSCM)
    • Fast Wake-up and Start-up
    • Backup Internal Oscillator
    • LPRC Oscillator
  • Power Management:
    • Low-Power Management Modes (Sleep, Idle, Doze)
    • Integrated Power-on Reset and Brown-out Reset
    • Debugger Development Support
    • In-Circuit and In-Application Programming
    • Simultaneous Debugging Support for Master and Slave Cores
    • Master Only Debug and Slave Only Debug Support
    • IEEE 1149.2 Compatible (JTAG) Boundary Scan
    • Trace Buffer and Run-Time Watch
Parametrics
Name
Value
Architecture
16-bit
Max CPU Speed (MHz)
100
CPU Speed (MIPS/DMIPS)
100
Program Memory Size (KB)
512
Multiple Flash Panels
Yes
Error Correction Code Program Flash
Yes
SRAM (KB)
48
Direct Memory Access Channels
6
Temperature Range (C)
-40 to 150
Operating Voltage Range (V)
3 to 3.6
Pin Count
64
Comparators
4
Analog Peripherals
4-A/D 34x12-bit @ 3500(ksps) 4-D/A 1x12-bit
UART
3
SPI
3
I2C
3
Timers
14 x 16-bit 6 x 32-bit
Motor Control PWM Outputs
24
SMPS PWM Outputs
24
Input Capture
12
Max PWM outputs (including complementary)
36
Number of PWM Time Bases
24
Output Compare Channels
12
Class B Hardware
Yes
Quadrature Encoder Interface
2
Configurable Cell Logic
8
Peripheral Trigger Generator
Yes
Peripheral Pin Select / Pin Muxing
Yes
Supported in MPLAB Code Configurator
Yes

Documents

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11/13/2013
204KB

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Development Environment

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Emulators & Debuggers
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Programmers
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MPLAB ICD 4 In-Circuit Debugger
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PICkit 3 In-Circuit Debugger
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MPLAB ICD 3 In-Circuit Debugger
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Demo & Evaluation Boards
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Explorer 16/32 Development Board
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dsPICDEM MCHV-2 Development System
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dsPICDEM MCHV-3 Development System
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dsPIC33CH512MP508 Motor Control PIM
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Software Libraries
16-bit CPU Self-test Library

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
DSPIC33CH512MP206-E/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33CH512MP206-I/PT
0.286700
2.487500
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33CH512MP206T-I/PT
0.286700
0.574667
64
TQFP
10x10x1mm
Matte Tin
e3
DSPIC33CH512MP206-E/MR
0.232400
0.350000
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33CH512MP206-I/MR
0.232400
0.350000
64
QFN
9x9x0.9mm
Matte Tin
e3
DSPIC33CH512MP206T-I/MR
0.232400
0.370303
64
QFN
9x9x0.9mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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