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ZL30117

SONET/SDH System Synchronizer

Status: In Production

Features:

  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
  • Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30117 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. The DPLL is capable of locking to one of three input references and provides a wide variety of synchronized output clocks and frame pulses.

Additional Features
  • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813
  • Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
  • Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
  • Supports automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth
  • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
  • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
Parametrics
Name
Value
Type
PDH/SDH
DPLL Bandwidth (Hz)
14 Hz, 28 Hz, or 890 Hz
Inputs
3
Diff Outputs
1
CMOS Outputs
2
Typical Jitter (12kHz-20MHz) fs RMS
OC-192/STM-64
Diff InputFreq Range
8 khz - 77.76 Mhz
Output Freq Range
8 khz - 77.76 MHz
NV Memory
N/A
NCO ppb
N/A
Align
2

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Data Sheets

  
262KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30117GGG2
0.313500
1.361539
64
LBGA
9x9x1.72mm
SAC305
e1
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Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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