RISC-V^® ISA for PolarFire^® FPGAs

RISC-V^® ISA for PolarFire^® FPGAs is a one-day course for engineers who are using PolarFire FPGAs to implement soft RISC-V (Mi-V processor core) designs. The class introduces the RISC-V Instruction Set Architecture (ISA), Microchip's RISC-V offerings and the RISC-V ecosystem. Hands-on lab exercises will show you how to implement and debug your RISC-V designs.

Please note: this class does not cover the embedded RISC-V processors that are available in PolarFire SoC FPGAs.

This class is taught virtually using WebEx^®

• Implement a RISC-V design targeting the PolarFire FPGA family
• Develop and debug firmware applications using Microchip's free SoftConsole software development environment

• Completion of Introduction to Libero^® SoC Design Suite course
• Completion of Introduction to PolarFire FPGAs course
• Familiarity with the FPGA design flow and microprocessor (MPU) code development

• The latest version of Libero SoC Design Suite installed with the working license file (Silver license or paid license)
• Installation of latest SoftConsole tool provided by Microchip
• One of the following kits; see FPGA Kits and Hardware for more information:
  • PolarFire Splash Kit
  • PolarFire SoC Discovery Kit
  • PolarFire SoC Icicle Kit

If you do not have one of these kits, you can still create the design and run the simulations, but you will not be able to program and debug your design.

Enroll for the course by completing the registration materials. Available dates are presented on the registration page.