Introduction to Libero^® SoC Design Suite

Introduction to Libero^® SoC Design Suite is a two-day course consisting of lectures and hands-on labs. This course will teach you how to use Libero SoC Design Suite to take a PolarFire^® FPGA-based design from concept to functional prototype. You can use VHDL or Verilog for the hands-on labs.

This class is taught virtually using WebEx^® 

• Create projects with Libero SoC Design Suite
• Use PolarFire FPGA IP generators and SmartDesign
• Generate and simulate testbenches using the QuestaSim Pro Simulator
• Use Libero SoC Design Suite's Enhanced Constraint Flow
• Synthesize with Synplify Pro^® ME
• Use the I/O Editor to make pin assignments and set I/O attributes
• Floorplan with ChipPlanner
• Create design layouts (place and route)
• Undergo static timing analysis with SmartTime and power analysis with SmartPower
• Generate back-annotated timing files and programming files
• Program the FPGA
• Debug with SmartDebug and Identify ME

• Experience with PCs and the Windows^® operating system

• The latest version of Libero SoC Design Suite installed with the working license file (Silver, Seminar or paid license)
• One of the following kits; see FPGA Kits and Hardware for more information:
  • PolarFire Splash Kit
  • PolarFire Evaluation Kit
  • PolarFire SoC Discovery Kit
  • PolarFire SoC Icicle Kit

If you do not have one of these kits, you can still create the design and run the simulations, but you will not be able to program and debug your design.

Enroll for the course by completing the registration materials. Available dates are presented on the registration page.