Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power
In this blog post, we’ll dive into the upcoming Mi-V RV32 v4.0, a 32-bit soft RISC-V processor launching in 2025. You’ll discover its key enhancements, including speed boosts, resource-efficient options and advanced safety features. We’ll explore its context within the RISC-V ecosystem, break down its major features and guide you on how to leverage this IP for your next project with Microchip’s FPGAs.

Imagine a rocket, meticulously engineered for efficiency, speed and reliability, ready to launch into the vast expanse of space. The Mi-V RV32 v4.0 soft RISC-V processor is much like that rocket, designed to propel embedded systems to new performance levels within our Field-Programmable Gate Array (FPGA) ecosystem. Just as a rocket adapts to varying payloads and missions, this processor’s configurability makes it a versatile powerhouse for applications from general-purpose to high-reliability real-time tasks.
In this blog post, we’ll dive into the upcoming Mi-V RV32 v4.0, a 32-bit soft RISC-V processor launching in 2025. You’ll discover its key enhancements, including speed boosts, resource-efficient options and advanced safety features. We’ll explore its context within the RISC-V ecosystem, break down its major features and guide you on how to leverage this IP for your next project with Microchip’s RT PolarFire®, RTG4, PolarFire and Igloo2 FPGAs.
The RISC-V architecture has transformed the semiconductor industry with its open-standard instruction set, enabling customizable and cost-effective processors. Since its debut in 2020, the Mi-V RV32 IP has been a cornerstone for our FPGA users, evolving through customer feedback and technological advancements. The upcoming v4.0 release reflects our commitment to pushing boundaries, integrating lessons from previous iterations to meet diverse application needs. As embedded systems demand higher performance and reliability, the Mi-V RV32 v4.0 is poised to lead in 2025, aligning with trends toward modular, scalable processor designs.
A block diagram of the upcoming Mi-V RV32 v4.0 processor IP is illustrated below. The core consists of a single order RISC-V 32-bit HART (HARdware Thread). V4.0 will add support for Atomic Memory Operations (AMO) in addition to the existing IMFC extensions. The HART has a dedicated Sub System featuring Caches and Tightly Coupled Memory (TCM) options as well as a range of integrated peripherals and AMBA Interfaces.
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Key Enhancements of Mi-V RV32 v4.0
Boosted Performance
The v4.0 targets up to a 30% speed increase over its predecessor, v3.1, through a redesigned pipeline that minimizes long paths and optimizes for FPGA implementation. This performance leap, configuration-dependent, ensures faster execution across most setups, making it ideal for compute-intensive embedded applications.
Low-Resource Configuration
For resource-constrained projects, a minimalist RV32I core option targets just 3000 Logic Elements resources in an RT PolarFire FPGA, while maintaining robust speed. This small-footprint configuration retains essential privilege specification features (CSRs), with potential for further optimization in future releases, catering to low-overhead embedded systems.
Enhanced Safety and Reliability
Safety-critical applications benefit from v4.0’s advanced features, including default Hamming 2 coding for all Finite State Machines (FSMs), with an optional Hamming 3 implementation for enhanced error correction. An integrated Watchdog Timer (WDT) and options for Error Correction Code (ECC) on RAM or synthesizable soft triple-module-redundant (TMR) registers further bolster reliability, ensuring robust operation in high-stakes environments such as space.
Comprehensive Feature Set
The Mi-V RV32 v4.0 supports RV32I with optional M, C, F and A extensions, alongside features like Tightly Coupled Memory (TCM) up to 256 KB, conditional branch prediction, and configurable Boot ROM. It offers flexible interfaces (dual AXI3/AXI4, AHB), 64-bit data support on memory interfaces and debugging options via JTAG or APB. Enhanced trigger capabilities, including up to four hardware breakpoints and watchpoints, add versatility for developers.
Want More?
The Mi-V RV32 v4.0 processor IP marks an important milestone for developers building on Microchip FPGAs. Pair it with the Mi-V Extendable Sub-System (ESS) for a seamless embedded solution and stay tuned for future Lockstep Controller IP and Trace IP suite enhancements. To explore how this processor IP can elevate your designs, visit Microchip’s RISC-V solutions page for detailed documentation and resources. For personalized guidance, contact our team at Microchip’s support portal.