Make the Most of Rad-Hard RTG4™ FPGAs With the Right Approach to Timing and Resets

Importance of Rad-Hard Technology

Field Programmable Gate Array (FPGA) development is complex enough when designing systems for use on Earth. But it’s a whole different ball game when you leave the atmosphere.

The harsh radiation of space can wreak havoc on computer systems and corrupt data. Rad-hard technology is a must when developing products for space. But these devices present their own brand of technical challenges, the stickiest of which include timing and resets.

You must consider timing penalties when using rad-hard parts. Internal block Random Access Memory (RAM) architecture and error correction features can slow down packets on their way through. Even just a few hundred picoseconds can present significant barriers to successful operation and user experience depending on what the end product is used for.

“If you need speeds above 100 megahertz, some of the rad-hard features can make this challenging,” says DornerWorks FPGA engineer Brian Douglas.

DornerWorks engineers have been developing products for space using our rad-hard RTG4 FPGAs.

Overcoming Timing Challenges in Space Products

Most developers want to design their FPGA system cleanly and free from inefficient resets. But that’s not always possible. Sometimes processes just don’t all line up to a clock edge. Ordinarily, this would warrant an “asynchronous” reset, but rad-hard parts complicate this assumption. The amount of resources available for resets are limited. NASA guidelines further recommend using only asynchronous resets.

“In space and aerospace applications or high reliability applications, you want asynchronous resets because you can cause a determined state whenever you need, without waiting for clocks,” Douglas says. “If I/O needs to be turned off, it can be turned off right now.”

In contrast, synchronous resets are generated by memory elements and aligned to a clock. And there’s a good reason they are not preferred in space applications.

“The problem with those resets is that if the clock is not running the reset doesn’t work,” Douglas says. “If you have an issue on a board, say the crystal locks up or the programmable logic-generated clocks have a problem and you can’t really reset the thing, that can be a problem for certain applications.”

So, why not both?

Our RTG4 FPGAs Enable Networking in Space

DornerWorks used our RTG4 FPGAs in a multi-layer Ethernet networking solution that will improve the quality of life for astronauts in space. The same technology can provide highly reliable data connections between instruments and on-board computers or enable a fleet of remote sensing satellites.

RTG4 FPGAs enable products that stand up to the harsh radiation of space.

Our engineers implemented a series of “synchronized asynchronous” resets, applying them sparingly to reduce inefficient resource utilization.

“It’s a slightly different paradigm than most people are used to,” Douglas says.

There is no direct path from fabric to a reset pin on a memory element within the RTG4 FPGA architecture. Register reset pins can be reached asynchronously from the device’s RGRESET blocks, but synchronous resets must be promoted to triple-modular redundancy dedicated reset resources to achieve proper resource utilization, timing and radiation mitigation.

This means that resets generated somewhere in the FPGA fabric can get in the way of other processes in the FPGA fabric.

“There’s obviously a limit,” Douglas says. “If you have multiple asynchronous resets you can end up basically blocking logic from being populated on some rows. Effectively you reduce your resource utilization by doing resets.”

Our system isn’t burdened by these challenges. Douglas and team opted for synchronous resets in the design and implemented them using the Libero^® SoC Design Suite software tools.

“There are some IP from Microchip that use asynchronous resets that are asserted asynchronously but de-asserted synchronously,” Douglas says. “The circuit is essentially asynchronous resets driven by a clocked memory element.”

Other Potential Applications

This is not the type of system that will control safety-critical components like engines or navigational equipment, but it does prove the flexibility and capability of rad-hard RTG4 FPGAs in the face of harsh radiation.

Most developers want to design their FPGA system cleanly and free from inefficient resets. But that’s not always possible. Sometimes processes just don’t all line up to a clock edge. Ordinarily this would warrant an “asynchronous” reset, but rad-hard parts complicate this assumption, while NASA guidelines further recommend using only asynchronous resets. Our approach, using Microchip’s RTG4 FPGAs and asynchronous resets that are asserted asynchronously but de-asserted synchronously, helps solve this problem.

Rad-hard parts are necessary to enable electronics in space. These parts must be protected from the physical impact of harsh radiation and must be able to prevent logic damage that could lead to equipment malfunction.

DornerWorks Space Switch on a Chip IP and Dev Kit features our RTG4 FPGAs and provides an accelerated path to developing products that make life easier for people working in the harshest conditions on Earth and in space.

As a Microchip Authorized Design Partner and Mi-V ecosystem partner, DornerWorks can help you implement your IP on state-of-the-art RTG4 FPGAs, RT PolarFire^® FPGAs, the PolarFire System-on-Chip (SoC) and many other hardware solutions from Microchip. Schedule a meeting with us when you are ready to turn your ideas into reality.

Learn more about FPGA development with hands-on resources from Microchip Makes.