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Libero® IDE

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Join us on Thursday, June 4th at 9 AM (Pacific Time).  Debugging software and hardware in isolation is no longer sufficient. Learn how unified debug workflows correlate software execution with hardware behavior in real time with our PolarFire® System-on-Chip (SoC) devices.

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Our Libero® Integrated Development Environment (IDE) software release for designing with our radiation-tolerant (rad-tolerant) FPGAs, antifuse FPGAs and legacy and discontinued Flash FPGAs manages the entire design flow from design entry, synthesis and simulation to place-and-route, timing and power analysis. 

For other FPGA families, please use refer to Libero SoC Design Suite versions v12.0 to later or Libero SoC Design Suite versions 11.10 and earlier (see Device Support section for details). 

Features

  • Powerful project and design flow management
  • Full suite of integrated design entry tools and methodologies:
  • SmartDesign graphical SoC design creation with automatic abstraction to HDL
  • IP core catalog and configuration
  • User-defined block creation flow for design reuse
  • Synplify Pro ME synthesis fully optimizes our FPGA device performance and area utilization
  • Synphony Model Compiler ME performs high-level synthesis optimizations within a Simulink® environment
  • ModelSim ME VHDL or Verilog behavioral, post-synthesis and post-layout simulation capability
  • Physical design implementation, floor planning, physical constraints and layout
  • Timing-driven and power-driven place-and-route
  • SmartTime environment for timing constraint management and analysis
  • SmartPower for providing comprehensive power analysis for actual and "what if" power scenarios
  • Interface to FlashPro programmers
  • Post-route on-chip debug tools and Identify ME debugging software for Flash designs using our FPGAs
  • Silicon Explorer II debugging software for antifuse designs with our FPGAs

Software and Documentation

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