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ZL30256

Jitter Attenuator

Status: In Production

Features:

  • Up to 3 independent DPLL channels
  • Excellent jitter performance of 180 fs RMS in 12 kHz to 20 MHz band meets jitter requirements of 10G/40G and 100G PHYs
  • Two programmable ultra-low jitter synthesizers generate any frequency from 1 Hz to 1045 MHz
  • One programmable general purpose synthesizer generates any clock from 1Hz to 180 MHz
  • Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
  • Up to four programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 1 kHz to 900 MHz and to clock plus sync pulse
  • Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 1 ppb with post holdover filter
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30256 is multi-channel high-performance, any-rate multiplier and jitter attenuator which simplifies board design by generating ultra-low-jitter clock signals from or attenuating clock signals while generating additional independent frequency families.With 3 independent jitter attenuating DPLL channels, the ability to create 5 different frequency families and best-in-class jitter performance, the ZL30256 can create complete clock-trees, improving design reliability, reducing bill of materials (BOM) cost, and simplifying design by replacing multiple PLLs and peripheral timing components.

Additional Features
  • Up to 3 independent DPLL channels
  • Excellent jitter performance of 180 fs RMS in 12 kHz to 20 MHz band meets jitter requirements of 10G/40G and 100G PHYs
  • Two programmable ultra-low jitter synthesizers generate any frequency from 1 Hz to 1045 MHz
  • One programmable general purpose synthesizer generates any clock from 1Hz to 180 MHz
  • 8 differential or 16 single ended (CMOS) ultra-low jitter outputs plus two general purpose CMOS outputs
  • Accepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs
  • Any input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)
  • Up to four programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 1 kHz to 900 MHz and to clock plus sync pulse
  • Automatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 1 ppb with post holdover filter
  • Easy Configuration and dynamic programming via SPI/I2C interface
  • Operates from a single crystal resonator or clock oscillator
Parametrics
Name
Value
Type
General Purpose
DPLLs or Paths
3
DPLL Bandwidth (Hz)
14 –470
Inputs
5 D/10 SE
Diff Outputs
8
CMOS Outputs
18
Low-Jitter Synthesizers
3
Typical Jitter (12kHz-20MHz) fs RMS
180
Diff InputFreq Range
1 kHz–1045 M
Output Freq Range
1 Hz–1045 M
NV Memory
Int EE
NCO ppb
0.0000035

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3323KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30256LFG7Q04N
0.195700
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
ZL30256LFG7
0.195700
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
ZL30256-LFG7-QA
0.195700
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
ZL30256LFG7Q05R
0.195700
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
ZL30256LFG7Q06T
0.195700
1.613636
80
VFLGA
11x11x1mm
NiAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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