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ZL30108

PDH/SDH System Synchronizer

Status: In Production

Features:

  • Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
  • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides a 19.44 MHz (SONET/SDH) clock output
  • Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
  • Provides automatic entry into Holdover and return from Holdover
  • Hitless reference switching
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards.  Measuring just 5 mm (millimeters) x 5 mm, the ZL30108 DPLL addresses dense line card "real estate" constraints. The device may be used in combination with Microchip's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment. For example, the ZL30108 DPLL and ZL30415 analog PLL provide an easy-to-implement, compact solution for OC-12/STM-4 line cards.

Additional Features
  • Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces
  • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs
  • Provides a 19.44 MHz (SONET/SDH) clock output
  • Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse
  • Provides automatic entry into Holdover and return from Holdover
  • Hitless reference switching
  • Provides lock and accurate reference fail indication
  • Loop filter bandwidth of 29 Hz or 14 Hz
  • Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications
  • Ultra Compact (5 mm x 5 mm) 32-pin QFN package
Parametrics
Name
Value
Type
PDH/SDH
DPLLs or Paths
1
DPLL Bandwidth (Hz)
29 Hz or 14 Hz
Inputs
2
CMOS Outputs
1
Typical Jitter (12kHz-20MHz) fs RMS
OC-3/ STM-1
Diff InputFreq Range
2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
Output Freq Range
19.44 MHz
NV Memory
N/A
NCO ppb
N/A
Align
2

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Data Sheets

  
691KB

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Dimension
Solder Composition
JEDEC Indicator
RoHS
China EFUP
ZL30108LDG1
0.070100
0.571429
32
VQFN
5x5x1mm
Matte Tin
e3
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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