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SY89874AU

Status: In Production

Features:

  • Integrated programmable clock divider and 1:2 fanout buffer
  • >2.5GHz fMAX
  • <250ps tr/tf
  • <15ps within-device skew
  • <1psRMS cycle-to-cycle jitter
  • <10psPP total jitter
  • Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; LVCMOS, LVTTL, CML, PECL, LVDS, and HSTL
  • TTL/CMOS inputs for select and reset
  • 100k EP-compatible LVPECL outputs
  • Parallel programming capability
  • Programmable divider ratios of 1, 2, 4, 8, and 16
  • Low-voltage operation 2.5V or 3.3V
  • Output disable function
  • -40°C to +85°C temperature range
  • Available in 16-pin (3mm x 3mm) QFN package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, LVDS or HSTL clock input signal and divide down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8, and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components.

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).Use the SY89874U version, which has a wider input range, to DC-couple low offset differential signals.

Additional Features
    • Integrated programmable clock divider and 1:2 fanout buffer
    • Guaranteed AC performance over temperature and voltage:
      • >2.5GHz fMAX
      • <250ps tr/tf
      • <15ps within-device skew
    • Low jitter design
      • <1psRMS cycle-to-cycle jitter
      • <10psPP total jitter
    • Unique input termination and VT pin for DC-coupled and AC-coupled Inputs; LVCMOS, LVTTL, CML, PECL, LVDS, and HSTL
    • TTL/CMOS inputs for select and reset
    • 100k EP-compatible LVPECL outputs
    • Parallel programming capability
    • Programmable divider ratios of 1, 2, 4, 8, and 16
    • Low-voltage operation 2.5V or 3.3V
    • Output disable function
    • -40°C to +85°C temperature range
    • Available in 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Description
÷1, ÷2, ÷4, ÷8, ÷16; 2 Outputs
Input
ANY
Output
LVPECL
Supply Voltage
2.5/3.3V
Max Freq (GHz)
2.5
Max Prop Delay (ps)
570
Icc (mA)
50
Max Within Device Skew (ps)
15
OE
True
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVPECL

Documents

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Data Sheet

06/24/2019
1306KB

Development tools data is currently unavailable.

RoHS Information

Part Number
Device Weight (g)
Shipping Weight (grams)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY89874AUMG
0.021300
0.050000
16
VQFN
3x3x1.00mm
NiPdAu
e4
SY89874AUMG-TR
0.021300
0.801700
16
VQFN
3x3x1.00mm
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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